/*
 * Copyright 2010 Allied Telesis.
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2002,2003, Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_ddr_sdram.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <flash.h>
#include <epi3.h>

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif

extern void local_bus_init(void);
#if !defined(CONFIG_SPD_EEPROM)
extern long int fixed_sdram(void);
#endif

#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f (void)
{
#if defined(CONFIG_PCI)
	volatile ccsr_pcix_t *pcix = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
#ifdef CONFIG_MPC85XX_PCI2
	volatile ccsr_pcix_t *pcix2 = (void *)(CONFIG_SYS_MPC85xx_PCIX2_ADDR);
#endif

        pcix->peer &= 0xffffffdf; /* disable master abort */
        pcix2->peer &= 0xffffffdf; /* disable master abort */
#endif

        return 0;
}
#endif

#ifdef CONFIG_MISC_INIT_R
int misc_init_r (void)
{
        /* turn off the fault LED */
        *((char*)(CONFIG_SYS_EPLD_BASE+0x42)) = 0x01;

	/* Disable the PHY LED buffer */
	*((char*)(CONFIG_SYS_EPLD_BASE+0xaf)) = 0x01;

	/* Put the management PHY into reset */
	*((char*)(CONFIG_SYS_EPLD_BASE+0xae)) = 0x00;

        /* wait 11ms 88E1111 datasheet requires 10ms */
        udelay(11000);

	/* Bring the management PHY out of reset */
	*((char*)(CONFIG_SYS_EPLD_BASE+0xae)) = 0x01;

	/* Enable the PHY LED buffer */
	*((char*)(CONFIG_SYS_EPLD_BASE+0xaf)) = 0x00;

        /* wait 5ms before accessing registers 88E1111 datasheet requires 5ms */
        udelay(5000);
        
#if 0 /* MW:TO_DO */
#ifndef CONFIG_SYS_NO_FLASH
	/* ICK! what a hack! this can sit here till we figure out what to do about
         * the new P30 'soft' block locking scheme
         */
        if (flash_info[0].sector_count == 259)
        {
                /* Only P30 has 259 blocks, so this is a good, err, easy way to detect it 
                 * Doing this every time on J3D would be *really* bad.
                 */
                if (*(u8 *)CONFIG_SYS_EPLD_BASE >= 7)
                {
                        /* 64MB x900 */
                        int i;
                        for (i = 0; i < 259; i++)
                                flash_real_protect(&flash_info[0], i, 0);
                        for (i = 0; i < 248; i++)
                                flash_real_protect(&flash_info[1], i, 0);
                }
                else
                {
                        /* 32MB x900 */
                        int i;
                        for (i = 0; i < 248; i++)
                                flash_real_protect(&flash_info[0], i, 0);
                }
        }
#endif /* CONFIG_SYS_NO_FLASH */
#endif

#ifdef CONFIG_DIAG_EPI3
        epi3_setmacaddr();
#endif
        return 0;
}
#endif

int checkboard (void)
{
	puts("Board: Allied Telesis x900\n");

#ifdef CONFIG_PCI
	printf("PCI1:  32 bit, %d MHz (compiled)\n",
	       CONFIG_SYS_CLK_FREQ / 1000000);
#ifdef CONFIG_MPC85XX_PCI2
	printf("PCI2:  32 bit, %d MHz (compiled)\n",
	       CONFIG_SYS_CLK_FREQ / 1000000);
#else
	printf("PCI2:  disabled\n");
#endif
#else
	printf("PCI1:  disabled\n");
	printf("PCI2:  disabled\n");
#endif

	/*
	 * Initialize local bus.
	 */
	local_bus_init();

	return 0;
}


phys_size_t
initdram(int board_type)
{
	long dram_size = 0;

	puts("Initializing\n");

#if 1
#if defined(CONFIG_DDR_DLL)
	{
		/*
		 * Work around to stabilize DDR DLL MSYNC_IN.
		 * Errata DDR9 seems to have been fixed.
		 * This is now the workaround for Errata DDR11:
		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
		 */
                volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

		gur->ddrdllcr = 0x81000000;
		asm("sync;isync;msync");
		udelay(200);
	}
#endif
#else
#if defined(CONFIG_DDR_DLL)
	{
	    volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	    uint temp_ddrdll = 0;

	    /*
	     * Work around to stabilize DDR DLL
	     */
	    temp_ddrdll = gur->ddrdllcr;
	    gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
	    asm("sync;isync;msync");
	}
#endif
#endif

#ifdef CONFIG_SPD_EEPROM
	dram_size = fsl_ddr_sdram();
	dram_size = setup_ddr_tlbs(dram_size / 0x100000);

	dram_size *= 0x100000;
#else
	dram_size = fixed_sdram();
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(dram_size);
#endif

	puts("       DDR: ");
	return dram_size;
}


/*
 * Initialize Local Bus
 */

void
local_bus_init(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);

	uint clkdiv;
	uint lbc_hz;
	sys_info_t sysinfo;

	/*
	 * Errata LBC11.
	 * Fix Local Bus clock glitch when DLL is enabled.
	 *
	 * If localbus freq is < 66MHz, DLL bypass mode must be used.
	 * If localbus freq is > 133MHz, DLL can be safely enabled.
	 * Between 66 and 133, the DLL is enabled with an override workaround.
	 */

	get_sys_info(&sysinfo);
	clkdiv = lbc->lcrr & LCRR_CLKDIV;
	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;

	if (lbc_hz < 66) {
		lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000;	/* DLL Bypass */

	} else if (lbc_hz >= 133) {
		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */

	} else {
		/*
		 * On REV1 boards, need to change CLKDIV before enable DLL.
		 * Default CLKDIV is 8, change it to 4 temporarily.
		 */
		uint pvr = get_pvr();
		uint temp_lbcdll = 0;

		if (pvr == PVR_85xx_REV1) {
			/* FIXME: Justify the high bit here. */
			lbc->lcrr = 0x10000004;
		}

		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
		udelay(200);

		/*
		 * Sample LBC DLL ctrl reg, upshift it to set the
		 * override bits.
		 */
		temp_lbcdll = gur->lbcdllcr;
		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
		asm("sync;isync;msync");
	}
}


#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
long int fixed_sdram (void)
{
  #ifndef CONFIG_SYS_RAMBOOT
	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);

	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
    #if defined (CONFIG_DDR_ECC)
	ddr->err_disable = 0x0000000D;
	ddr->err_sbe = 0x00ff0000;
    #endif
	asm("sync;isync;msync");
	udelay(500);
    #if defined (CONFIG_DDR_ECC)
	/* Enable ECC checking */
	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
    #else
	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
    #endif
	asm("sync; isync; msync");
	udelay(500);
  #endif
	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif	/* !defined(CONFIG_SPD_EEPROM) */


#if defined(CONFIG_PCI)
/*
 * Initialize PCI Devices, report devices found.
 */


static struct pci_controller hose;

#endif	/* CONFIG_PCI */


void
pci_init_board(void)
{
#ifdef CONFIG_PCI
	pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}


#if defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
	int node, tmp[2];
#ifdef CONFIG_PCI
	const char *path;
#endif

	ft_cpu_setup(blob, bd);

	node = fdt_path_offset(blob, "/aliases");
	tmp[0] = 0;
	if (node >= 0) {
#ifdef CONFIG_PCI
		path = fdt_getprop(blob, node, "pci0", NULL);
		if (path) {
			tmp[1] = hose.last_busno - hose.first_busno;
			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
		}
#endif
	}
}
#endif

/* atl_bootrom_board_attached()
 *
 * used by bootmenu to determine weather or not to print
 * option '5' (EPROM) in upgrade bootloader menu
 */

int atl_bootrom_board_attached(void)
{
	return !(*(u8 *)0xFF0000E0 & 0x1);
}

/* atl_get_offset_from_base()
 *
 * the way u-boot works at the moment is that there's a flash
 * 'base' (0xF8000000) and special flash blocks (env, epi3, bootcode)
 * reside at the top of flash so if the size increases, then all of those
 * blocks end up moving upwards which is icky as hell but it's (thanks to NST)
 * the way things work on this product.
 *
 * This function returns the amount the special blocks have moved up if the
 * the flash size is larger than 32MB, if the flash size is 32MB then that
 * is considered to be 'base' if that makes sense?
 */

u32 atl_get_offset_from_base(void)
{
	/* Currently, if the CPLD version is greater than 7, we assume it's 64MB
	 * Needs to be clearer in future.
	 */
	if (*(u8 *)CONFIG_CPLD_VERSION >= 7)
		return 0x2000000; /* 64MB system, so change is 32MB */
	else
		return 0x0; /* 32MB system, no change, use _BASE Macros in config header */
}

/* The functions below are used in place of the usual constant macros used in the
 * device config header file, this system mostly works except for the environment
 * code which had to be hacked up to allow for a "moving" environment
 */

/* atl_get_flash_increment()
 *
 * If the flash driver was a bit smarter this wouldn't be needed.
 * Basically it tells the flash driver how much memory to jump by before
 * looking for the next flash chip.
 */

u32 atl_get_flash_increment(void)
{
	if (*(u8 *)CONFIG_CPLD_VERSION >= 7)
		return 0x2000000; /* 32MB */
	else
		return 0x1000000; /* 16MB */
}

/* atl_get_epi3_location()
 *
 * Get the location of the epi3 block
 */

u32 atl_get_epi3_location(void)
{
	return (CONFIG_EPI3_LOCATION_BASE + atl_get_offset_from_base());
}

/* atl_get_jffs2_part_size()
 *
 * Get the size of the main JFFS2 partition, this also changes size when the 
 * flash has increased, obviously.
 */

u32 atl_get_jffs2_part_size(void)
{
	return (CONFIG_JFFS2_PART_SIZE_BASE + atl_get_offset_from_base());
}

/* atl_get_uboot_flash_base()
 * 
 * Get the actual location of U-Boot in flash
 */

u32 atl_get_uboot_flash_base(void)
{
	return (CONFIG_UBOOT_FLASH_BASE_BASE + atl_get_offset_from_base());
}

/* atl_get_env_addr()
 *
 * Get location of U-Boot environement. ENV code was hacked a little to make this work
 */

u32 atl_get_env_addr(void)
{
	return (CONFIG_ENV_ADDR_BASE + atl_get_offset_from_base());
}

#ifdef CONFIG_MMC_SPI
/* SD card functions */

u8 sdcard_is_present(void)
{
	u8 sdcard_present;
	sdcard_present = ((*(volatile u8 *)0xFF000091) & 0x01) == 0;
	return sdcard_present;
}

u8 sdcard_has_changed(void)
{
       u8 sdcard_changed = ((*(volatile u8 *)0xFF000095) & 0x01) != 0;

       *(volatile u8 *)0xFF000095 = 0x00;
       *(volatile u8 *)0xFF000095 = 0x01;

       return sdcard_changed;
}

void sdcard_check_changed(void)
{
	/* Not needed */
}

u8 sdcard_write_protected(void)
{
	u8 protect_on;
	protect_on = ((*(volatile u8 *)0xFF000091) & 0x02) != 0;
	return protect_on;
}

void sdcard_select(u8 select)
{
	volatile ccsr_cpm_t *im_cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;

	if (select)
	{
		im_cpm->im_cpm_iop.pdatd &= ~0x00001000;
	}
	else
	{
		im_cpm->im_cpm_iop.pdatd |= 0x00001000;
	}
}

#endif
