/*
 * Board config file for ATL AR415
 *
 * Allied Telesis Labs
 */

#ifndef __CONFIG_H
#define __CONFIG_H

//#define DEBUG 1
/*
 * High Level Configuration Options
 * (easy to change)
 */
 
#define CONFIG_THIS_DEVICE 	5
#define CONFIG_COMPATIBLE_DEVICES 	\
{ 					\
	{ 275, "AT-AR415S" },		\
	{ 276, "AT-AR415S-DC" },	\
	{ 0, NULL }			\
}

#define CONFIG_UBOOT_SIZE_VARIES
 
#define CPU_ID_STR		"MPC8248"

#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
#define CONFIG_CPM2		1	/* Has a CPM2 */

#undef CONFIG_PCI 

#define CONFIG_HAVE_OWN_RESET 1 	/* We have our own reset routine in board/atlar415/atlar415.c*/
/*
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 *
 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 * defined elsewhere (for example, on the cogent platform, there are serial
 * ports on the motherboard which are used for the serial console - see
 * cogent/cma101/serial.[ch]).
 */
#define	CONFIG_CONS_ON_SCC 1		/* define if console on SCC */
#undef	CONFIG_CONS_ON_SMC 		/* define if console on SMC */
#undef	CONFIG_CONS_NONE		/* define if console on something else*/
#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
#undef	CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
#define	CONFIG_CONS_EXTC_RATE	9600	/* SMC/SCC ext clk rate in Hz */
#define	CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/

/*
 * select ethernet configuration
 *
 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC)
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 * from CONFIG_COMMANDS to remove support for networking.
 */
#undef		CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
#define	CONFIG_ETHER_ON_FCC1
#undef		CONFIG_ETHER_NONE		/* define if ether on something else */
#define 	CONFIG_ETHER_INDEX	1	/* which channel for ether	*/
#define	CONFIG_RESET_PHY_R /* define to call phy_reset routine*/
#define CONFIG_MII
#define CFG_PHY_ADDR 17

#define CFG_CMXFCR_MASK	0xFFFF0000
#define CFG_CMXFCR_VALUE	0x263d0000
#define CFG_FCC_PSMR		0x16000080
#define CFG_CPMFCR_RAMTYPE	0x00000000

/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#define CONFIG_8260_CLKIN	66666666	/* in Hz */

#define CFG_NS16550_CLK 3686400 /* HAAAAAAAAACK!!!!! Bootmenu looks for this macro */

#include <configs/atl-std-opts.h>

#define CONFIG_COMMANDS         ( CONFIG_GENERIC_COMMANDS ) 

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
#undef	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
#define	CONFIG_KGDB_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
#define	CONFIG_KGDB_EXTC_RATE	9600	/* serial ext clk rate in Hz */
#define	CONFIG_KGDB_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
# if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC)
#define CONFIG_KGDB_BAUDRATE	9600	/* speed to run kgdb serial port at */
# else
#define CONFIG_KGDB_BAUDRATE	9600	/* speed to run kgdb serial port at */
# endif
#endif


#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_early_init_f */

/*
 * Miscellaneous configurable options
 */

#define	CFG_PROMPT	"AR415> "	/* Monitor Command Prompt	*/
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS	32		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/



/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFF000000
#define CFG_DEFAULT_IMMR CFG_IMMR

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Hard Reset Configuration Words
 *
 * if you change bits in the HRCW, you must also change the CFG_*
 * defines for the various registers affected by the HRCW e.g. changing
 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 */
#define CFG_HRCW_MASTER 0x08660258
/* No slaves */
#define CFG_HRCW_SLAVE1	0
#define CFG_HRCW_SLAVE2	0
#define CFG_HRCW_SLAVE3	0
#define CFG_HRCW_SLAVE4	0
#define CFG_HRCW_SLAVE5	0
#define CFG_HRCW_SLAVE6	0
#define CFG_HRCW_SLAVE7	0

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */

#define CONFIG_JFFS2_PART_OFFSET 0x200000
#define CONFIG_JFFS2_PART_SIZE  0xE00000
    

#define	CFG_SDRAM_BASE		0
#define CFG_FLASH_BASE		0xFC000000	/* flash on m/b */
#define	CFG_MONITOR_BASE	TEXT_BASE

#define CONFIG_DIAGMEM_BASE 	0x01000000

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
#undef	CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
#define CFG_FLASH_CFI                         /* The flash is CFI compatible  */

#define CFG_ENV_ADDR		0xfc0c0000 /* Addr of Environment Sector */
#define CFG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
#define CFG_ENV_SIZE		0x2000

#define CONFIG_EPI3_SIZE        0x00020000
#define CONFIG_EPI3_LOCATION    0xfc0e0000

#define CONFIG_UBOOT_SIZE 	0x40000
#define CONFIG_UBOOT_FLASH_BASE	0xfc000000

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
#endif

/*-----------------------------------------------------------------------
 * HIDx - Hardware Implementation-dependent Registers			 2-11
 *-----------------------------------------------------------------------
 * HID0 also contains cache control - initially enable both caches and
 * invalidate contents, then the final state leaves only the instruction
 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 * but Soft reset does not.
 *
 * HID1 has only read-only information - nothing to set.
 */
#define CFG_HID0_INIT		0
#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)

#define CFG_HID2	0

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register					 5-5
 *-----------------------------------------------------------------------
 * turn on Checkstop Reset Enable
 */
#define CFG_RMR		RMR_CSRE

/*-----------------------------------------------------------------------
 * BCR - Bus Configuration					 4-25
 *-----------------------------------------------------------------------
 */
//#define CFG_BCR		BCR_EBM
#define CFG_BCR		0

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				 4-31
 *-----------------------------------------------------------------------
 */
//#define CFG_SIUMCR	(SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)
#define CFG_SIUMCR 0x09240000

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				 4-35
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 */
#define CFG_SYPCR 0

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control			 4-40
 *-----------------------------------------------------------------------
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 */
#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
//#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
#define CFG_PISCR	0

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control					 9-8
 *-----------------------------------------------------------------------
 * Ensure DFBRG is Divide by 4
 */
#define CFG_SCCR	(SCCR_DFBRG00)

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration				13-7
 *-----------------------------------------------------------------------
 */
#define CFG_RCCR	0


/*
 * Init Memory Controller:
 *
 *
 * (the *_SIZE vars must be a power of 2)
 */

#define CFG_CMA_CS0_BASE	TEXT_BASE	/* EPROM */
#define CFG_CMA_CS0_SIZE	(1 << 20)
#if 0
#define CFG_CMA_CS2_BASE	0x10000000	/* Local Bus SDRAM */
#define CFG_CMA_CS2_SIZE	(16 << 20)
#endif

/*
 * CS0 maps the EPROM on the cpu module
 * Set it for 10 wait states, address CFG_MONITOR_BASE and size 1M
 *
 * Note: We must have already transferred control to the final location
 * of the EPROM before these are used, because when BR0/OR0 are set, the
 * mirror of the eprom at any other addresses will disappear.
 */

#define CFG_OR0_PRELIM	0xFFF00C84
#define CFG_BR0_PRELIM	0xFFF01101

#define CFG_BR1_PRELIM	0x00000043
#define CFG_OR1_PRELIM	0xFE002EC0	/* RAM */

#define CFG_BR2_PRELIM	0xFC001001
#define CFG_OR2_PRELIM	0xFE000C84	/* FLASH */

#define CFG_BR4_PRELIM 	0xFE100801
#define CFG_OR4_PRELIM 	0xFFF00E66	/* PIC */

#define CFG_BR7_PRELIM 	0xFE301001
#define CFG_OR7_PRELIM 	0xFFF00874 	/* CPLD */


#define CFG_MPTPR 	0x1500
#define CFG_OR1 	0xFE002EC0
#define CFG_PSDMR 	0xC24AB662
#define CFG_PSRT 	0x45

//#define CFG_ALLOC_DPRAM
#define CONFIG_MPC8272_FAMILY 1


/*
 * CS2 enables the Local Bus SDRAM on the CPU Module
 *
 * Will leave this unset for the moment, because a) my CPU module has no
 * SDRAM installed (it is optional); and b) it will require programming
 * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
 * if you can't test it.
 */

#if 0
/* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, ??? */
#define CFG_BR0_PRELIM	((CFG_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
/* mask size CFG_CMA_CS2_SIZE, CS time normal, ??? */
#define CFG_OR2_PRELIM	((~(CFG_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
#endif

#endif	/* __CONFIG_H */
