/*
 * Copyright 2010 Allied Telesis.
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2002,2003, Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_ddr_sdram.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <flash.h>
#include <epi3.h>

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif

#ifdef CONFIG_MK_AR570S
extern int ar570s_dx160_setup(void);
#endif

void local_bus_init(void);
#if !defined(CONFIG_SPD_EEPROM)
long int fixed_sdram(void);
#endif

#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f (void)
{
#if defined(CONFIG_PCI)
	volatile ccsr_pcix_t *pcix = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
#ifdef CONFIG_MPC85XX_PCI2
	volatile ccsr_pcix_t *pcix2 = (void *)(CONFIG_SYS_MPC85xx_PCIX2_ADDR);
#endif

        pcix->peer &= 0xffffffdf; /* disable master abort */
#ifdef CONFIG_MPC85XX_PCI2
        pcix2->peer &= 0xffffffdf; /* disable master abort */
#endif
#endif

	return 0;
}
#endif

#ifdef CONFIG_MISC_INIT_R
int misc_init_r (void)
{
	volatile ccsr_cpm_t *cpm = (void *)(CONFIG_SYS_MPC85xx_CPM_ADDR);

	/* disable the phy */
	cpm->im_cpm_iop.pdata &= ~0x00200000;
	udelay(1000);

	/* enable the phy */
	cpm->im_cpm_iop.pdata |= 0x00200000;
	udelay(10);


	/* turn off the fault LED */
/* 	*((char*)(CONFIG_SYS_EPLD_BASE+0x42)) = 0x01; */

	/* Bring the management PHY out of reset */
/* 	*((char*)(CONFIG_SYS_EPLD_BASE+0xae)) = 0x01; */

	/* Enable the PHY LED buffer */
/* 	*((char*)(CONFIG_SYS_EPLD_BASE+0xaf)) = 0x01; */

	/* wait 5ms before accessing registers 88E1111 datasheet requires 5ms */
	udelay(5000);

#ifdef CONFIG_DIAG_EPI3
	epi3_setmacaddr();
#endif

#ifdef CONFIG_MK_AR570S
	/* De-assert SKIP_INITn (ie de-assert SKIP_INIT) */
	*((char *)(CONFIG_SYS_CPLD_BASE + 0x10)) = 0x01;
	udelay(100);
	/* Wait about 100ms for the reset to complete */
	*((char *)(CONFIG_SYS_CPLD_BASE + 0x1)) = 0x00;
	udelay(100000);
	/* Bring DX160 out of reset */
	*((char *)(CONFIG_SYS_CPLD_BASE + 0x1)) = 0x01;
	udelay(250);

	/* Bring phys out of reset */
	*((char *)(CONFIG_SYS_CPLD_BASE + 0x2)) = 0x01;
	*((char *)(CONFIG_SYS_CPLD_BASE + 0x3)) = 0x01;
	*((char *)(CONFIG_SYS_CPLD_BASE + 0x4)) = 0x01;
	*((char *)(CONFIG_SYS_CPLD_BASE + 0x5)) = 0x01;
#endif

	return 0;
}
#endif

#ifdef CONFIG_LAST_STAGE_INIT
int last_stage_init(void)
{
#ifdef CONFIG_MK_AR570S
	/* Setup switch chip */
	ar570s_dx160_setup();
#endif
	return 0;
}
#endif

int checkboard (void)
{
	puts("Board: Allied Telesis AR550S\n");

#ifdef CONFIG_PCI
	printf("PCI1:  32 bit, %d MHz (compiled)\n",
	       CONFIG_SYS_CLK_FREQ / 1000000);
#ifdef CONFIG_MPC85XX_PCI2
	printf("PCI2:  32 bit, %d MHz (compiled)\n",
	       CONFIG_SYS_CLK_FREQ / 1000000);
#else
	printf("PCI2:  disabled\n");
#endif
#else
	printf("PCI1:  disabled\n");
	printf("PCI2:  disabled\n");
#endif

	/*
	 * Initialize local bus.
	 */
	local_bus_init();

	return 0;
}


phys_size_t
initdram(int board_type)
{
	long dram_size = 0;

	puts("Initializing\n");

#if 1
#if defined(CONFIG_DDR_DLL)
	{
		/*
		 * Work around to stabilize DDR DLL MSYNC_IN.
		 * Errata DDR9 seems to have been fixed.
		 * This is now the workaround for Errata DDR11:
		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
		 */
                volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

		gur->ddrdllcr = 0x81000000;
		asm("sync;isync;msync");
		udelay(200);
	}
#endif
#else
#if defined(CONFIG_DDR_DLL)
	{
	    volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
		uint temp_ddrdll = 0;

		/*
		 * Work around to stabilize DDR DLL
		 */
		temp_ddrdll = gur->ddrdllcr;
		gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
		asm("sync;isync;msync");
	}
#endif
#endif

#ifdef CONFIG_SPD_EEPROM
	dram_size = fsl_ddr_sdram();
	dram_size = setup_ddr_tlbs(dram_size / 0x100000);

	dram_size *= 0x100000;
#else
	dram_size = fixed_sdram();
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(dram_size);
#endif

	puts("       DDR: ");
	return dram_size;
}


/*
 * Initialize Local Bus
 */

void
local_bus_init(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);

	uint clkdiv;
	uint lbc_hz;
	sys_info_t sysinfo;

	/*
	 * Errata LBC11.
	 * Fix Local Bus clock glitch when DLL is enabled.
	 *
	 * If localbus freq is < 66MHz, DLL bypass mode must be used.
	 * If localbus freq is > 133MHz, DLL can be safely enabled.
	 * Between 66 and 133, the DLL is enabled with an override workaround.
	 */

	get_sys_info(&sysinfo);
	clkdiv = lbc->lcrr & LCRR_CLKDIV;
	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;

	if (lbc_hz < 66) {
		lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000;	/* DLL Bypass */

	} else if (lbc_hz >= 133) {
		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */

	} else {
		/*
		 * On REV1 boards, need to change CLKDIV before enable DLL.
		 * Default CLKDIV is 8, change it to 4 temporarily.
		 */
		uint pvr = get_pvr();
		uint temp_lbcdll = 0;

		if (pvr == PVR_85xx_REV1) {
			/* FIXME: Justify the high bit here. */
			lbc->lcrr = 0x10000004;
		}

		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
		udelay(200);

		/*
		 * Sample LBC DLL ctrl reg, upshift it to set the
		 * override bits.
		 */
		temp_lbcdll = gur->lbcdllcr;
		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
		asm("sync;isync;msync");
	}
}


#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
long int fixed_sdram (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	int ram_size, cs0_bnds, cs0_config;

	/* Detect ram size from board pin strapping */
	switch ((gur->gpporcr >> 30) & 0x3) {
	case 1:
		ram_size = 128;
		cs0_bnds = 0x00000008;
			cs0_config = 0x80000101; /* 13 rows, 9 columns */
		break;
	case 2:
		ram_size = 256;
		cs0_bnds = 0x00000010;
			cs0_config = 0x80000102; /* 13 rows, 10 columns */
		break;
	case 3:
		ram_size = 512;
		cs0_bnds = 0x00000020;
			cs0_config = 0x80000202; /* 14 rows, 10 columns */
		break;
	case 0:
	default:
		ram_size = 64;
		cs0_bnds = 0x00000004;
			cs0_config = 0x80000001; /* 12 rows, 9 columns */
		break;
	}

#ifndef CONFIG_SYS_RAMBOOT
	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);

	ddr->cs0_config = cs0_config;
	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
#ifdef CONFIG_MK_AR570S
	ddr->cs0_bnds = 7;
	ddr->timing_cfg_1 = 0x36342221;
	ddr->sdram_mode = 0x00020062;
	ddr->sdram_interval = 0x04120100;
#else
	ddr->cs0_bnds = cs0_bnds;
	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
#endif
#if defined (CONFIG_DDR_ECC)
	ddr->err_disable = 0x0000000D;
	ddr->err_sbe = 0x00ff0000;
#endif
	asm("sync;isync;msync");
	udelay(500);
#if defined (CONFIG_DDR_ECC)
	/* Enable ECC checking */
	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
#else
	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
#endif
	asm("sync; isync; msync");
	udelay(500);
#endif
	return ram_size * 1024 * 1024;
}
#endif	/* !defined(CONFIG_SPD_EEPROM) */


#if defined(CONFIG_PCI)
/*
 * Initialize PCI Devices, report devices found.
 */


static struct pci_controller hose;

#endif	/* CONFIG_PCI */


void
pci_init_board(void)
{
#ifdef CONFIG_PCI
	pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}


#if defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
	int node, tmp[2];
#ifdef CONFIG_PCI
	const char *path;
#endif

	ft_cpu_setup(blob, bd);

	node = fdt_path_offset(blob, "/aliases");
	tmp[0] = 0;
	if (node >= 0) {
#ifdef CONFIG_PCI
		path = fdt_getprop(blob, node, "pci0", NULL);
		if (path) {
			tmp[1] = hose.last_busno - hose.first_busno;
			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
		}
#endif
	}
}
#endif


/* atl_bootrom_board_attached()
 *
 * used by bootmenu to determine weather or not to print
 * option '5' (EPROM) in upgrade bootloader menu
 */

int atl_bootrom_board_attached(void)
{
	return 0; /*!(*(u8 *)0xFF0000E0 & 0x1);*/
}

/* atl_get_offset_from_base()
 */

u32 atl_get_offset_from_base(void)
{
	return 0x0; /* 32MB system, no change, use _BASE Macros in config header */
}

/* The functions below are used in place of the usual constant macros used in the
 * device config header file, this system mostly works except for the environment
 * code which had to be hacked up to allow for a "moving" environment
 */

/* atl_get_flash_increment()
 */

u32 atl_get_flash_increment(void)
{
	return 0x1000000; /* 16MB */
}

/* atl_get_epi3_location()
 *
 * Get the location of the epi3 block
 */

u32 atl_get_epi3_location(void)
{
	return (CONFIG_EPI3_LOCATION_BASE + atl_get_offset_from_base());
}

/* atl_get_jffs2_part_size()
 *
 * Get the size of the main JFFS2 partition, this also changes size when the
 * flash has increased, obviously.
 */

u32 atl_get_jffs2_part_size(void)
{
	return (CONFIG_JFFS2_PART_SIZE_BASE + atl_get_offset_from_base());
}

/* atl_get_uboot_flash_base()
 *
 * Get the actual location of U-Boot in flash
 */

u32 atl_get_uboot_flash_base(void)
{
	return (CONFIG_UBOOT_FLASH_BASE_BASE + atl_get_offset_from_base());
}

/* atl_get_env_addr()
 *
 * Get location of U-Boot environement. ENV code was hacked a little to make this work
 */

u32 atl_get_env_addr(void)
{
	return (CONFIG_ENV_ADDR_BASE + atl_get_offset_from_base());
}
