/*
 * Copyright 2011 Allied Telesis.
 */

/* Keyhole for register access */
#define DX160_WRITE_ADDR_MSB            0x00
#define DX160_WRITE_ADDR_LSB            0x01
#define DX160_WRITE_DATA_MSB            0x02
#define DX160_WRITE_DATA_LSB            0x03
#define DX160_READ_ADDR_MSB             0x04
#define DX160_READ_ADDR_LSB             0x05
#define DX160_READ_DATA_MSB             0x06
#define DX160_READ_DATA_LSB             0x07
#define DX160_READ_WRITE_STATUS         0x1f

/* Read/Write status */
#define DX160_SMI_READ_RDY              (1 << 0)
#define DX160_SMI_WRITE_DONE            (1 << 1)

/* Configuration for blatting registers at boot */
struct dx160_config_reg {
	u32 addr;
	u32 mask;
	u32 data;
};

int dx160_reg_read(char *devname, int smi_addr, u32 reg_addr, u32 *reg_data);
int dx160_reg_write(char *devname, int smi_addr, u32 reg_addr, u32 reg_data);
int dx160_mii_write(char *devname, int smi_addr, u8 phy_addr, u8 reg_addr,
		    u16 reg_data);
int dx160_mii_read(char *devname, int smi_addr, u8 phy_addr, u8 reg_addr,
		   u16 *reg_data);
int dx160_config(char *devname, u8 smi_addr,
		 struct dx160_config_reg const *config);
void dx160_read_all(void);
