/*
 * (C) Copyright 2001-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Modified during 2001 by
 * Advanced Communications Technologies (Australia) Pty. Ltd.
 * Howard Walker, Tuong Vu-Dinh
 *
 * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
 * Added support for the 16M dram simm on the 8260ads boards
 *
 * (C) Copyright 2003-2004 Arabella Software Ltd.
 * Yuli Barcohen <yuli@arabellasw.com>
 * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
 *
 * Copyright (c) 2005 MontaVista Software, Inc.
 * Vitaly Bordug <vbordug@ru.mvista.com>
 * Added support for PCI.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
#include <asm/m8260_pci.h>
#include <i2c.h>
#include <spd.h>
#include <asm/mmu.h>
#include <miiphy.h>
#ifdef CONFIG_PCI
#include <pci.h>
#endif

/*
 * I/O Port configuration table
 *
 * if conf is 1, then that port pin will be configured at boot time
 * according to the five values podr/pdir/ppar/psor/pdat for that entry
 */

#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)

const iop_conf_t iop_conf_tab[4][32] = {

    /* Port A configuration */
    {	/*	      conf      ppar psor pdir podr pdat */
	/* PA31 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL   */
	/* PA30 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS   */
	/* PA29 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER */
	/* PA28 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN */
	/* PA27 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV */
	/* PA26 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER */
	/* PA25 */ { 1,          0,   0,   1,   0,   0 }, /* PA25 */
	/* PA24 */ { 1,          0,   0,   1,   0,   0 }, /* PA24 */
	/* PA23 */ { 1,          0,   0,   1,   0,   0 }, /* PA23 */
	/* PA22 */ { 1,          0,   0,   1,   0,   0 }, /* PA22 */
	/* PA21 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
	/* PA20 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
	/* PA19 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
	/* PA18 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
	/* PA17 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
	/* PA16 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
	/* PA15 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
	/* PA14 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
	/* PA13 */ { 1,          0,   0,   0,   0,   0 }, /* PA13 */
	/* PA12 */ { 1,          0,   0,   0,   0,   0 }, /* PA12 */
	/* PA11 */ { 1,          0,   0,   0,   0,   0 }, /* PA11 */
	/* PA10 */ { 1,          0,   0,   0,   0,   0 }, /* PA10 */
	/* PA9  */ { 1,          1,   0,   1,   0,   0 }, /* SMC2 TXD */
	/* PA8  */ { 1,          1,   0,   0,   0,   0 }, /* SMC2 RXD */
	/* PA7  */ { 1,          0,   0,   1,   0,   0 }, /* PA7 */
	/* PA6  */ { 1,          0,   0,   0,   0,   0 }, /* PA6 */
	/* PA5  */ { 1,          0,   0,   1,   0,   0 }, /* PA5 */
	/* PA4  */ { 1,          0,   0,   1,   0,   0 }, /* PA4 */
	/* PA3  */ { 1,          0,   0,   1,   0,   0 }, /* PA3 */
	/* PA2  */ { 1,          0,   0,   1,   0,   0 }, /* PA2 */
	/* PA1  */ { 1,          0,   0,   0,   0,   0 }, /* PA1 */
	/* PA0  */ { 1,          0,   0,   1,   0,   0 }  /* PA0 */
    },

    /* Port B configuration */
    {   /*	      conf      ppar psor pdir podr pdat */
	/* PB31 */ { 1,   		 0,   0,   0,   0,   0 }, /* GPIO */
	/* PB30 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV */
	/* PB29 */ { CFG_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN */
	/* PB28 */ { 1,			 0,   0,   0,   0,   0 }, /* GPIO */
	/* PB27 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL */
	/* PB26 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS */
	/* PB25 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
	/* PB24 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
	/* PB23 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
	/* PB22 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
	/* PB21 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
	/* PB20 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
	/* PB19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
	/* PB18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
	/* PB17 */ { 1,   		 0,   0,   0,   0,   0 }, /* pin doesn't exist */
	/* PB16 */ { 1,   		 0,   0,   0,   0,   0 }, /* pin doesn't exist */
	/* PB15 */ { 1,   		 0,   0,   0,   0,   0 }, /* pin doesn't exist */
	/* PB14 */ { 1,   		 0,   0,   0,   0,   0 }, /* pin doesn't exist */
	/* PB13 */ { 1,   		 0,   0,   0,   0,   0 }, /* pin doesn't exist */
	/* PB12 */ { 1,   		 0,   0,   0,   0,   0 }, /* pin doesn't exist */
	/* PB11 */ { 1,   		 0,   0,   0,   0,   0 }, /* pin doesn't exist */
	/* PB10 */ { 1,   		 0,   0,   0,   0,   0 }, /* pin doesn't exist */
	/* PB9  */ { 1,   		 0,   0,   0,   0,   0 }, /* pin doesn't exist */
	/* PB8  */ { 1,   		 0,   0,   0,   0,   0 }, /* pin doesn't exist */
	/* PB7  */ { 1,   		 0,   0,   0,   0,   0 }, /* pin doesn't exist */
	/* PB6  */ { 1,   		 0,   0,   0,   0,   0 }, /* pin doesn't exist */
	/* PB5  */ { 1,   		 0,   0,   0,   0,   0 }, /* pin doesn't exist */
	/* PB4  */ { 1,			 0,   0,   0,   0,   0 }, /* pin doesn't exist */
	/* PB3  */ { 1,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
	/* PB2  */ { 1,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
	/* PB1  */ { 1,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
	/* PB0  */ { 1,          0,   0,   0,   0,   0 }  /* pin doesn't exist */
    },

    /* Port C */
    {   /*	      conf      ppar psor pdir podr pdat */
	/* PC31 */ { 1,          0,   0,   0,   0,   0 }, /* PC31 */
	/* PC30 */ { 1,          0,   0,   0,   0,   0 }, /* PC30 */
	/* PC29 */ { 1,          0,   0,   1,   0,   0 }, /* PC29 */
	/* PC28 */ { 1,          0,   0,   1,   0,   0 }, /* PC28 */
	/* PC27 */ { 1,          1,   0,   0,   0,   0 }, /* PC27 */
	/* PC26 */ { 1,          0,   0,   0,   0,   0 }, /* PC26 */
	/* PC25 */ { 1,          1,   0,   0,   0,   0 }, /* PC25 */
	/* PC24 */ { 1,          1,   0,   0,   0,   0 }, /* PC24 */
	/* PC23 */ { 1,          1,   0,   0,   0,   0 }, /* PC23 */
	/* PC22 */ { 1,  	 0,   0,   0,   0,   0 }, /* FCC1 MII Tx Clock (CLK10) */
	/* PC21 */ { 1,  	 1,   0,   0,   0,   0 }, /* FCC1 MII Rx Clock (CLK11) */
	/* PC20 */ { 1,          0,   0,   1,   0,   0 }, /* PC20 */
	/* PC19 */ { 1,          0,   0,   1,   0,   0 }, /* GPIO  */
	/* PC18 */ { 1,          1,   0,   0,   0,   0 }, /* CLK14 */
	/* PC17 */ { 1,  	 0,   0,   1,   0,   0 }, /* GPIO */
	/* PC16 */ { 1,  	 1,   0,   0,   0,   0 }, /* FCC2 MII Tx Clock (CLK16) */
	/* PC15 */ { 1,          0,   0,   0,   0,   0 }, /* PC15 -- Console CTS*/
	/* PC14 */ { 1,          1,   0,   0,   0,   0 }, /* PC14 -- Console DCD*/
	/* PC13 */ { 1,          0,   0,   1,   0,   0 }, /* PC13 -- Console DTR*/
	/* PC12 */ { 1,          0,   0,   1,   0,   0 }, /* PC12 */
	/* PC11 */ { 1,          1,   0,   0,   0,   0 }, /* PC11 SCC3*/
	/* PC10 */ { 1,          1,   0,   0,   0,   0 }, /* PC10 SCC3*/
	/* PC9  */ { 1,          0,   0,   1,   0,   0 }, /* PC9  */
	/* PC8  */ { 1,          0,   0,   0,   0,   0 }, /* PC8 */
	/* PC7  */ { 1,          0,   0,   1,   0,   0 }, /* PC7 */
	/* PC6  */ { 1,          0,   0,   1,   0,   0 }, /* PC6 */
	/* PC5  */ { 1,          0,   0,   1,   0,   0 }, /* PC5 */
	/* PC4  */ { 1,          0,   0,   0,   0,   0 }, /* PC4 */
	/* PC3  */ { 1,          0,   0,   0,   0,   0 }, /* PC3 */
	/* PC2  */ { 1,          0,   0,   0,   0,   0 }, /* PC2 */
	/* PC1  */ { 1,          0,   0,   0,   0,   0 }, /* PC1 */
	/* PC0  */ { 1,          0,   0,   0,   0,   0 }, /* PC0 */
    },

    /* Port D */
    {   /*	      conf ppar psor pdir podr pdat */
	/* PD31 */ {   1,   0,   0,   0,   0,   0   }, /* SFA */
	/* PD30 */ {   1,   0,   0,   0,   0,   0   }, /* SFA */
	/* PD29 */ {   1,   0,   0,   0,   0,   0   }, /* PD29 -- Console RTS */
	/* PD28 */ {   1,   0,   0,   0,   0,   0   }, /* PD28 */
	/* PD27 */ {   1,   0,   0,   0,   0,   0   }, /* PD27 */
	/* PD26 */ {   1,   0,   0,   0,   0,   0   }, /* PD26 */
	/* PD25 */ {   1,   1,   0,   0,   0,   0   }, /* PD25 */
	/* PD24 */ {   1,   1,   0,   1,   0,   0   }, /* PD24 */
	/* PD23 */ {   1,   1,   0,   1,   0,   0   }, /* PD23 */
	/* PD22 */ {   1,   1,   1,   0,   0,   0   }, /* PD22 */
	/* PD21 */ {   1,   1,   1,   0,   0,   0   }, /* PD21 */
	/* PD20 */ {   1,   1,   1,   0,   0,   0   }, /* PD20 */
	/* PD19 */ {   1,   0,   0,   1,   0,   0   }, /* PD19 */
	/* PD18 */ {   1,   0,   0,   1,   0,   0   }, /* PD18 */
	/* PD17 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
	/* PD16 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXPRTY */
	/* PD15 */ {   1,   0,   0,   1,   0,   0   }, /* I2C SDA */
	/* PD14 */ {   1,   0,   0,   1,   0,   0   }, /* I2C SCL */
	/* PD13 */ {   1,   0,   0,   0,   0,   0   }, /* PD13 */
	/* PD12 */ {   1,   0,   0,   0,   0,   0   }, /* PD12 */
	/* PD11 */ {   1,   0,   0,   0,   0,   0   }, /* PD11 */
	/* PD10 */ {   1,   0,   0,   0,   0,   0   }, /* PD10 */
	/* PD9  */ {   1,   0,   0,   1,   0,   0   }, /* SMC1 TXD */
	/* PD8  */ {   1,   0,   0,   0,   0,   0   }, /* SMC1 RXD */
	/* PD7  */ {   1,   0,   0,   1,   0,   0   }, /* PD7 */
	/* PD6  */ {   1,   0,   0,   0,   0,   0   }, /* PD6 */
	/* PD5  */ {   1,   0,   0,   0,   0,   0   }, /* PD5 */
	/* PD4  */ {   1,   0,   0,   0,   0,   0   }, /* PD4 */
	/* PD3  */ {   1,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD2  */ {   1,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD1  */ {   1,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
        /* PD0  */ {   1,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
    }
};

void reset_phy (void)
{
#ifdef CONFIG_MII

	atl_ar440_miiphy_init();

#endif /* CONFIG_MII */

}

#ifdef CONFIG_PCI
typedef struct pci_ic_s {
	unsigned long pci_int_stat;
	unsigned long pci_int_mask;
}pci_ic_t;
#endif

int board_early_init_f (void)
{
        unsigned short * led_reg;
        unsigned short * reset_reg;

#ifdef CONFIG_PCI
//	volatile pci_ic_t* pci_ic = (pci_ic_t *) CFG_PCI_INT;

	/* mask alll the PCI interrupts */
//	pci_ic->pci_int_mask |= 0xfff00000;
#endif

	led_reg = (unsigned short *)0xfe300002;
        reset_reg = (unsigned short *)0xfe300006;
	
        *led_reg = 0x8000; // System LED off

        *reset_reg = 0x0000;

        udelay(100);
        
        *reset_reg = 0x0002; // Un-reset Switch

        udelay(250);

	return 0;
}

#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)

long int initdram (int board_type)
{
        unsigned short memsize;
      
        unsigned int memsizes[] =
                                { 
                                    32, 
                                    64, 
                                    128, 
                                    256 
                                };
 
        unsigned long ors[] = 
                                {     
                                    0xFE002EC0, /* 32MB */
                                    0xFC002CC0, /* 64MB */
                                    0xF8002B00, /* 128MB */
                                    0xF0002900  /* 256MB */
                                };
        unsigned long psdmrs[] = 
                                {
                                    0xC24AB662, /* 32MB */
                                    0xC34EB662, /* 64MB */
                                    0xC32EB662, /* 128MB */
                                    0xC432B662,  /* 256MB */
                                };

        unsigned long pstrs[] = 
                                {
                                    0x16,       /* 32MB */
                                    0x16,       /* 64MB */
                                    0x3,        /* 128MB */
                                    0x3         /* 256MB */
                                };

        unsigned long mptptrs[] =
                                {
                                    0x4200,     /* 32MB */
                                    0x4200,     /* 64MB */
                                    0xBD00,     /* 128MB */
                                    0xBD00      /* 256MB */
                                };

        unsigned long psdmr;
        
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8260_t *memctl = &immap->im_memctl;
	volatile uchar *ramaddr, c = 0xff;
	int i;
        
        memsize = *(unsigned short *)0xfe300004; /* Read mem size from CPLD */
        memsize &= 0x3;

        psdmr = psdmrs[memsize];
        
	memctl->memc_mptpr = mptptrs[memsize];

	/* Init 60x bus SDRAM */

        memctl->memc_psrt = pstrs[memsize];
	memctl->memc_or1 = ors[memsize];
	memctl->memc_br1 = CFG_SDRAM_BASE | 0x00000043;
	ramaddr = (uchar *) CFG_SDRAM_BASE;
	
        memctl->memc_psdmr = psdmr | 0x28000000;	/* Precharge all banks */
	*ramaddr = c;
	memctl->memc_psdmr = psdmr | 0x08000000;	/* CBR refresh */
	
        for (i = 0; i < 8; i++)
		*ramaddr = c;

	memctl->memc_psdmr = psdmr | 0x18000000;	/* Mode Register write */
	*ramaddr = c;
	memctl->memc_psdmr = psdmr | 0x40000000;	/* Refresh enable */
	*ramaddr = c;


	/* return total 60x bus SDRAM size */
	return (memsizes[memsize] * 1024 * 1024);
}

int checkboard (void)
{
#ifdef CONFIG_ALLIEDTELESIS_OUTPUT
	if (!console_full_output())
		return 0;
#endif /* CONFIG_ALLIEDTELESIS_OUTPUT */
	puts ("Board: Allied Telesis Labs AR440S\n");
	return 0;
}

#ifdef CONFIG_PCI

static struct pci_config_table pci_ar440_config_table[] = {
  { 
    0x8086, 0x1229, PCI_ANY_ID, PCI_ANY_ID, /* Intel Pro/100 */ 
    13, PCI_ANY_ID, pci_cfgfunc_config_device, 
    { 0x80000000, 0x80000000, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } 
  },
  { 0x1022, 0x2000, PCI_ANY_ID, PCI_ANY_ID, /* AMD PCnet 32 */
    13, PCI_ANY_ID, pci_cfgfunc_config_device, 
    { 0xA0000000, 0x80000000, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } 
  }
};

static struct pci_controller hose = {
  config_table: pci_ar440_config_table,
};


extern void pci_mpc8250_init(struct pci_controller *);

void pci_init_board(void)
{

  pci_mpc8250_init(&hose);
}
#endif

int
do_reset (void)
{
	unsigned short * suicudeReg ;

	suicudeReg  = (unsigned short  * )0xfe300000 ;
	*suicudeReg = 1;

//	should not get here
	while( 1 ) ;
}

int atl_bootrom_board_attached(void)
{
	return 1;
}
