/*
 * Board config for ATL AR440
 *
 * Allied Telesis Labs
 */

/*
 * Config header file for Allied Telesis Labs AR415
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_THIS_DEVICE 	6
#define CONFIG_COMPATIBLE_DEVICES 	\
{ 					\
	{ 226, "AT-AR440S" },		\
	{ 227, "AT-AR441S" },		\
	{ 228, "AT-AR442S" },		\
	{ 229, "AT-AR443S" },		\
	{ 230, "Reserved" },		\
	{ 231, "Reserved" },		\
	{ 0, NULL }			\
}

/*
 * Options for special ATL Boards (for making one off builds)
 */
//#define USE_ETH_PIC /* If this is turned on, ability to use FCC Ethernet/PCI Ethernet is lost */
//#define USE_ETH_PAC
//#define DEBUG

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_DIAGMEM_BASE	0x1000000

#define CONFIG_ATLAR440
#define CPU_ID_STR		"MPC8272"

#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
#define CONFIG_CPM2		1	/* Has a CPM2 */

#if defined(USE_ETH_PAC) && !defined(USE_ETH_PIC)
#define CONFIG_PCI
#endif
//#define CONFIG_PCI_SCAN_SHOW

#define CONFIG_HAVE_OWN_RESET 1 	/* We have our own reset routine in board/atlar415/atlar415.c*/

/*
 * select serial console configuration
 *
 * 16C550 for AR440
 * 
 */

#define CONFIG_CONS_INDEX     1
#undef  CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE    1
#define CFG_NS16550_CLK         3686400


#define CFG_NS16550_COM1        (0xFE000000)
  

/*
 * select ethernet configuration
 *
 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC)
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 * from CONFIG_COMMANDS to remove support for networking.
 */


#undef	CONFIG_ETHER_NONE		/* define if ether on something else */

#ifdef USE_ETH_PIC

#define CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
#define	CONFIG_ETHER_INDEX	3	/* which channel for ether	*/
#define CFG_CMXSCR_VALUE        CMXSCR_RS3CS_CLK8 | CMXSCR_TS3CS_CLK7

#else

#define CONFIG_NET_MULTI
//#define CONFIG_EEPRO100

#ifdef USE_ETH_PAC
#define CONFIG_PCNET
//#define PCNET_HAS_PROM
#define CONFIG_PCNET_79C972
#define CONFIG_PCNET_79C973
#endif

#define CONFIG_ETHER_ON_FCC
#define	CONFIG_ETHER_ON_FCC2
#define CONFIG_ETHER_INDEX      2
#define CONFIG_MII
#define	CONFIG_RESET_PHY_R /* define to call phy_reset routine*/
#define CFG_PHY_ADDR 17
#define CFG_CMXFCR_MASK2        0xFFFFFFFF
#define CFG_CMXFCR_VALUE2	0x013D0000
#define CFG_FCC_PSMR		0x14400080
#define CFG_CPMFCR_RAMTYPE	0x00000000

#endif


#define _IO_BASE 0x000000
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#define CONFIG_8260_CLKIN	100000000	/* in Hz */

#include <configs/atl-std-opts.h>

#define CONFIG_COMMANDS         ( CONFIG_GENERIC_COMMANDS )

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>


#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
#undef	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
#define	CONFIG_KGDB_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
#define	CONFIG_KGDB_EXTC_RATE	9600	/* serial ext clk rate in Hz */
#define	CONFIG_KGDB_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
# if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC)
#define CONFIG_KGDB_BAUDRATE	9600	/* speed to run kgdb serial port at */
# else
#define CONFIG_KGDB_BAUDRATE	9600	/* speed to run kgdb serial port at */
# endif
#endif

#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */

#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_early_init_f */

/*
 * Miscellaneous configurable options
 */
#define	CFG_PROMPT	"AR440> "	/* Monitor Command Prompt	*/


#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFF000000
#define CFG_DEFAULT_IMMR CFG_IMMR

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Hard Reset Configuration Words
 *
 * if you change bits in the HRCW, you must also change the CFG_*
 * defines for the various registers affected by the HRCW e.g. changing
 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 */
#define CFG_HRCW_MASTER 0x08660258
/* No slaves */
#define CFG_HRCW_SLAVE1	0
#define CFG_HRCW_SLAVE2	0
#define CFG_HRCW_SLAVE3	0
#define CFG_HRCW_SLAVE4	0
#define CFG_HRCW_SLAVE5	0
#define CFG_HRCW_SLAVE6	0
#define CFG_HRCW_SLAVE7	0

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */

#define CONFIG_JFFS2_PART_OFFSET 0x200000
#define CONFIG_JFFS2_PART_SIZE  0xE00000
    

#define	CFG_SDRAM_BASE		0
#define	CFG_FLASH_BASE		0xFC000000	/* flash on m/b */
#define	CFG_MONITOR_BASE	TEXT_BASE
#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define	CFG_MALLOC_LEN		(2048 << 10)	/* Reserve 2 MB for malloc()*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
#undef	CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
#define CFG_FLASH_CFI                         /* The flash is CFI compatible  */

#define CFG_ENV_ADDR		0xfc0c0000 /* Addr of Environment Sector */
#define CFG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
#define CFG_ENV_SIZE		0x2000

#define CONFIG_EPI3_SIZE        0x00020000
#define CONFIG_EPI3_LOCATION    0xfc0e0000

#define CONFIG_UBOOT_SIZE	0x40000
#define CONFIG_UBOOT_SIZE_VARIES
#define CONFIG_UBOOT_FLASH_BASE	CFG_FLASH_BASE

#define CONFIG_UBOOT_ROM_BASE   0xfc000000



/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
#endif

/*-----------------------------------------------------------------------
 * HIDx - Hardware Implementation-dependent Registers			 2-11
 *-----------------------------------------------------------------------
 * HID0 also contains cache control - initially enable both caches and
 * invalidate contents, then the final state leaves only the instruction
 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 * but Soft reset does not.
 *
 * HID1 has only read-only information - nothing to set.
 */

#ifndef HID0_IFEM
#define HID0_IFEM  (1<<7)
#endif


#define CFG_HID0_INIT		0

#ifdef USE_ETH_PAC

#define CFG_HID0_FINAL          0
#define CONFIG_CHANGE_CACHE_SETTINGS_AT_LAST_MINUTE
#define CFG_HID0_BOOT		(HID0_ICE | HID0_IFEM | HID0_ABE | HID0_DCE)

#else

#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)

#endif

#define CFG_HID2	        0


/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register					 5-5
 *-----------------------------------------------------------------------
 * turn on Checkstop Reset Enable
 */
#define CFG_RMR		RMR_CSRE

/*-----------------------------------------------------------------------
 * BCR - Bus Configuration					 4-25
 *-----------------------------------------------------------------------
 */
//#define CFG_BCR		BCR_EBM
#define CFG_BCR		0

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				 4-31
 *-----------------------------------------------------------------------
 */
//#define CFG_SIUMCR	(SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)
#define CFG_SIUMCR 0x09240000

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				 4-35
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 */
#define CFG_SYPCR 0

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control			 4-40
 *-----------------------------------------------------------------------
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 */
#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
//#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
#define CFG_PISCR	0

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control					 9-8
 *-----------------------------------------------------------------------
 * Ensure DFBRG is Divide by 4
 */
#define CFG_SCCR	(SCCR_DFBRG00)

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration				13-7
 *-----------------------------------------------------------------------
 */
#define CFG_RCCR	0


/*
 * Init Memory Controller:
 *
 *
 * (the *_SIZE vars must be a power of 2)
 */

#define CFG_CMA_CS0_BASE	TEXT_BASE	/* EPROM */
#define CFG_CMA_CS0_SIZE	(1 << 20)
#if 0
#define CFG_CMA_CS2_BASE	0x10000000	/* Local Bus SDRAM */
#define CFG_CMA_CS2_SIZE	(16 << 20)
#endif

/*
 * CS0 maps the EPROM on the cpu module
 * Set it for 10 wait states, address CFG_MONITOR_BASE and size 1M
 *
 * Note: We must have already transferred control to the final location
 * of the EPROM before these are used, because when BR0/OR0 are set, the
 * mirror of the eprom at any other addresses will disappear.
 */

#define CFG_BR0_PRELIM		0xFFF01101
#define CFG_OR0_PRELIM		0xFFF00C84

#define CFG_BR1_PRELIM		0x00000043
#define CFG_OR1_PRELIM		0xFC002CC0	/* RAM */

#define CFG_BR2_PRELIM		0xFC001001
#define CFG_OR2_PRELIM		0xFE000C84	/* FLASH */

#define CFG_BR3_PRELIM          0xFE000801
#define CFG_OR3_PRELIM          0xFFF00C44      /* UART */

#define CFG_BR4_PRELIM 	        0xFE100801
#define CFG_OR4_PRELIM 	        0xFFF00E66	/* PIC */

#define CFG_BR5_PRELIM          0xFE100801      
#define CFG_OR5_PRELIM          0xFFF00886      /* DSL - Not confirmed */

#define CFG_BR7_PRELIM 	        0xFE301001
#define CFG_OR7_PRELIM 	        0xFFF00874 	/* CPLD */


/* BAT DEFINES. Not currently used because mpc8260 start.S doesn't look at these, 
 * left in here anyway in case I can be arsed implementing code to use this 
 */

#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
    
#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_11 | BATL_MEMCOHERENCE)
#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)

#define CFG_IBAT2L	(0xFFF00000 | BATL_MEMCOHERENCE | BATL_PP_10)
#define CFG_IBAT2U	(0xFFF00000 | BATU_BL_1M | BATU_VS | BATU_VP)

#define CFG_DBAT0L	CFG_IBAT0L
#define CFG_DBAT0U	CFG_IBAT0U

#define CFG_DBAT1L	CFG_IBAT1L
#define CFG_DBAT1U	CFG_IBAT1U

#define CFG_DBAT2L	CFG_IBAT2L
#define CFG_DBAT2U	CFG_IBAT2U

/* Current arbitrary mammoth PCI size eats up 3 BATs */

#define CFG_DBAT3L 	(0x80000000 |BATL_WRITETHROUGH | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE | BATL_PP_10)
#define CFG_DBAT3U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_IBAT3L	CFG_DBAT3L
#define CFG_IBAT3U	CFG_DBAT3U

#define CFG_DBAT4L 	(0x90000000 |BATL_WRITETHROUGH | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE | BATL_PP_10)
#define CFG_DBAT4U	(0x90000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_DBAT5L 	(0xA0000000 |BATL_WRITETHROUGH | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE | BATL_PP_10)
#define CFG_DBAT5U	(0xA0000000 | BATU_BL_64M | BATU_VS | BATU_VP)


//#define CFG_ALLOC_DPRAM
#define CONFIG_MPC8272_FAMILY 1
//#define CONFIG_MPC8272 1


/* PCI Memory map (if different from default map */
#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE		/* Local base */
#define CFG_PCI_SLV_MEM_BUS		0x00000000		/* PCI base */
#define CFG_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
				 PICMR_PREFETCH_EN)
				 
/*
 * These are the windows that allow the CPU to access PCI address space.
 * All three PCI master windows, which allow the CPU to access PCI
 * prefetch, non prefetch, and IO space (see below), must all fit within
 * these windows.
 */

/*
 * Master window that allows the CPU to access PCI Memory (prefetch).
 * This window will be setup with the second set of Outbound ATU registers
 * in the bridge.
 */

#define CFG_PCI_MSTR_MEM_LOCAL	0x80000000          /* Local base */
#define CFG_PCI_MSTR_MEM_BUS	0x80000000          /* PCI base   */
#define	CFG_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
#define CFG_PCI_MSTR_MEM_SIZE	0x10000000          /* 256MB */
#define CFG_POCMR0_MASK_ATTRIB	(POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)

/*
 * Master window that allows the CPU to access PCI Memory (non-prefetch).
 * This window will be setup with the second set of Outbound ATU registers
 * in the bridge.
 */

#define CFG_PCI_MSTR_MEMIO_LOCAL    0x90000000          /* Local base */
#define CFG_PCI_MSTR_MEMIO_BUS      0x90000000          /* PCI base   */
#define CFG_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
#define CFG_PCI_MSTR_MEMIO_SIZE     0x10000000          /* 256MB */
#define CFG_POCMR1_MASK_ATTRIB      (POCMR_MASK_256MB | POCMR_ENABLE)

/*
 * Master window that allows the CPU to access PCI IO space.
 * This window will be setup with the first set of Outbound ATU registers
 * in the bridge.
 */

#define CFG_PCI_MSTR_IO_LOCAL       0xA0000000          /* Local base */
#define CFG_PCI_MSTR_IO_BUS         0xA0000000          /* PCI base   */
#define CFG_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
#define CFG_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
#define CFG_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)


/* PCIBR0 - for PCI IO*/
#define CFG_PCI_MSTR0_LOCAL		CFG_PCI_MSTR_IO_LOCAL		/* Local base */
#define CFG_PCIMSK0_MASK		~(CFG_PCI_MSTR_IO_SIZE - 1U)	/* Size of window */
/* PCIBR1 - prefetch and non-prefetch regions joined together */
#define CFG_PCI_MSTR1_LOCAL		CFG_PCI_MSTR_MEM_LOCAL
#define CFG_PCIMSK1_MASK		~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U)



/*
 * CS2 enables the Local Bus SDRAM on the CPU Module
 *
 * Will leave this unset for the moment, because a) my CPU module has no
 * SDRAM installed (it is optional); and b) it will require programming
 * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
 * if you can't test it.
 */

#if 0
/* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, ??? */
#define CFG_BR0_PRELIM	((CFG_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
/* mask size CFG_CMA_CS2_SIZE, CS time normal, ??? */
#define CFG_OR2_PRELIM	((~(CFG_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
#endif



#endif	/* __CONFIG_H */
