/*
 * x510.h
 * Graeme Campbell
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* BCM53000 Address map */
#define BCM53000_SDRAM		0x00000000 /* 0-128MB Physical SDRAM */
#define BCM53000_SDRAM_SWAP	0x10000000 /* Byteswapped Physical SDRAM */
#define BCM53000_SDRAM2		0x80000000 /* Large 256MB SDRAM region */
#define BCM53000_PCI_MEM	0x08000000 /* Host Mode PCI mem space (128MB)*/
#define BCM53000_PCI_DMA	0x40000000 /* Client Mode PCI mem space (1GB)*/
#define BCM53000_ENUM		0x18000000 /* Beginning of core enum space */
#define BCM53000_FLASH		0x1fc00000 /* Flash region 0 for MIPS boot */
#define BCM53000_FLASH2		0x1c000000 /* Flash region 1 (60MB) */
#define BCM53000_FLASH3		0x20000000 /* Large 256MB flash region */

/*
 * TLB map to access PCIE/DDR2/flash beyond KSEG
 *
 *  PCIE1
 *      0x40000000 -> 0x47ffffff    physical
 *      0xe0000000 -> 0xe7ffffff    virtual (uncached)
 *      0xc0000000 -> 0xc7ffffff    virtual (cached)
 *      length: 128MB
 *
 *  Flash
 *      0x20000000 -> 0x2fffffff    physical
 *      0x30000000 -> 0x3fffffff    virtual (uncached)
 *      0x10000000 -> 0x1fffffff    virtual (cached)
 *      length: 256MB
 *
 *  DDR2
 *      0x80000000 -> 0x9fffffff    physical
 *      0x60000000 -> 0x7fffffff    virtual (uncached)
 *      0x40000000 -> 0x5fffffff    virtual (cached)
 *      length: 512MB
 */
#define TLB_PCIE1_PHYS			BCM53000_PCI_DMA
#define TLB_PCIE1_VIRT_UNCACHED		0xe0000000
#define TLB_PCIE1_VIRT_CACHED		0xc0000000
#define TLB_PCIE1_SIZE			128*1024*1024
#define TLB_PCIE1_PAGESIZE		64*1024*1024
#define TLB_PCIE1_PAGEMASK		0x07FFE000
#define TLB_FLASH_PHYS			BCM53000_FLASH3
#define TLB_FLASH_VIRT_UNCACHED		0x30000000
#define TLB_FLASH_VIRT_CACHED		0x10000000
#define TLB_FLASH_SIZE			256*1024*1024
#define TLB_FLASH_PAGESIZE		256*1024*1024
#define TLB_FLASH_PAGEMASK		0x1FFFE000
#define TLB_SDRAM_PHYS			BCM53000_SDRAM2
#define TLB_SDRAM_VIRT_UNCACHED		0x60000000
#define TLB_SDRAM_VIRT_CACHED		0x40000000
#define TLB_SDRAM_SIZE			512*1024*1024
#define TLB_SDRAM_PAGESIZE		256*1024*1024
#define TLB_SDRAM_PAGEMASK		0x1FFFE000

#define SI_SDRAM_BASE		0x80000000  /* Physical SDRAM */
#define SI_PCI_MEM		0x08000000  /* Host Mode sb2pcitranslation0 (64 MB) */
#define SI_PCI1_MEM		0x40000000  /* Host Mode sb2pcitranslation0 (64 MB) */
#define SI_PCI_MEM_SZ		(64 * 1024 * 1024)
#define SI_PCI_CFG		0x0c000000  /* Host Mode sb2pcitranslation1 (64 MB) */
#define SI_PCI1_CFG		0x44000000  /* Host Mode sb2pcitranslation1 (64 MB) */


/* Below is a brief description of what is where in memory while uboot is running
 * on our MIPS environment
 *
 *	All addresses are from the kseg0 view of RAM
 *
 *	0x80001000-0x806FFFFF (~7MB)
 *	Linux kernel binary is loaded into this address
 *	by the boot_alliedware_package function from the DIAGMEM load point.
 *	The linux kernel is typically only about 3MB therefore doesn't use all
 *	of this space.
 *	0x80800000-0x80FFFFFF (8MB)
 *	C Code in uboot has it's stack in this location
 *	The kernel command line and bd_t struct are loaded just before this location
 *	when the kernel is kicked off.
 *	0x81000000-0x82FFFFFF (32MB)
 *	DIAGMEM location. This is use for a number of tasks where some data needs to be
 *	temporarily stored. i.e. when a package is TFTP downloaded, it gets stored here
 *	0x83000000-0x83080000 (512KB)
 *	A temporary copy of the boot rom is stored here for loading from boot rom to flash
 *	Hopefully this should be able to removed in the future
 *
 *	These boundaries are guidelines and are not enforced by *anything* at present.
 */

#define CONFIG_MIPS32		1	/* MIPS 4Kc CPU core	*/
#define CONFIG_X510		1	/* on a x510 boards designed by SJ */
#define CONFIG_DIAGNOSTICS
#define CONFIG_DIAG_NOR_FLASH
#define CONFIG_DIAG_EPI3
#define CONFIG_DIAG_USB
#define CONFIG_BOOTMENU
#define CONFIG_SYS_STDALONE_TFTP

#define CONFIG_THIS_DEVICE	10
#define CONFIG_COMPATIBLE_DEVICES 	\
{					\
	{ 369, "x510-28GTX" },		\
	{ 370, "x510-28GPX" },		\
	{ 371, "x510-28GSX" },		\
	{ 372, "x510-52GTX" },		\
	{ 373, "x510-52GPX" },		\
	{ 0, NULL }			\
}


/* Serial Port */
#define CONFIG_CONS_INDEX     1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		x510_serial_base_clock()

#define CONFIG_SYS_NS16550_COM1		(0xB8000300)
#define CONFIG_SYS_NS16550_COM2		(0xB8000400)

#define CONFIG_BAUDRATE			9600

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */

#include <configs/atl-std-opts.h>
#undef CONFIG_CMD_DATE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_USB

#include <config_cmd_default.h>
/*
 * Miscellaneous configurable options
 */
#define CONFIG_ENV_OVERWRITE
#define	CONFIG_SYS_LONGHELP				/* undef to save memory      */
#define	CONFIG_SYS_PROMPT		"x510> "	/* Monitor Command Prompt    */
#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size   */
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */

#define CONFIG_SYS_INIT_RAM_LOCK_MIPS    1

#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024

#undef CONFIG_SYS_HZ
#define CONFIG_SYS_HZ			1000
#define CONFIG_SYS_MIPS_TIMER_FREQ	(x510_system_counter_freq()/2)

#define CONFIG_SYS_SDRAM_BASE		0x80000000	/* K0 remap of 128MB of lower memory RAM */
#define CONFIG_DIAG_RAM_START		TLB_SDRAM_VIRT_UNCACHED
#define CONFIG_DIAG_RAM_SKIP_SIZE	0x00800000

#define CONFIG_SYS_MEMTEST_START	0x00200000
#define CONFIG_SYS_MEMTEST_END		0x00800000

#define CONFIG_MISC_INIT_R

#define CONFIG_ETH_SWITCH		/* Boot from switch ports */
#define CONFIG_NET_MULTI		/* Multi ethernet cards support */

#define CONFIG_LZMA		1

/*
 * PCI
 */
#define CONFIG_PCI		1	/* Enable PCI/PCIE */
#define CONFIG_PCIE1		1	/* PCIE controller */
#define CONFIG_PCI_SCAN_SHOW		/* show devices on bus		*/

/* PCI MEMORY MAP section */
#define CONFIG_SYS_PCI0_MEM_BASE	BCM53000_PCI_DMA
#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)

#define CONFIG_PCIE_MEM			0x08000000  /* Host Mode sb2pcitranslation0 (64 MB) */
#define CONFIG_PCIE1_MEM		0x40000000  /* Host Mode sb2pcitranslation0 (64 MB) */
#define CONFIG_PCIE_MEM_SZ		(64 * 1024 * 1024)
#define CONFIG_PCIE_CFG			0x0c000000  /* Host Mode sb2pcitranslation1 (64 MB) */
#define CONFIG_PCIE1_CFG		0x44000000  /* Host Mode sb2pcitranslation1 (64 MB) */
#define CONFIG_PCIE_DMA_H32		0x80000000  /* PCIE Client Mode sb2pcitranslation2
						     * (2 ZettaBytes), high 32 bits */
#define CONFIG_PCIE1_DMA_H32		0xc0000000  /* PCIE Client Mode sb2pcitranslation2
						     * (2 ZettaBytes), high 32 bits */

/* PCI I/O MAP section */
#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
#define CONFIG_SYS_PCI0_IO_SIZE	_16M
#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
#define CONFIG_SYS_PCI1_IO_SIZE	_16M

#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000
#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000


/*
 * I2C
 */
#define CONFIG_HARD_I2C			/* I2C with hardware support*/
#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * USB/EHCI
 */
#ifdef CONFIG_CMD_USB
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
#define CONFIG_USB_EHCI							/* Enable EHCI USB support */
#define CONFIG_USB_EHCI_BCMA					/* on Broadcom AMBA bus */
#define CONFIG_EHCI_DCACHE
#define CONFIG_EHCI_DESC_BIG_ENDIAN
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
/*#define CONFIG_ISO_PARTITION*/

#endif /* CONFIG_CMD_USB */

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define PHYS_FLASH_1		TLB_FLASH_VIRT_UNCACHED /* Flash Bank #1 */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
#define CONFIG_SYS_FLASH_SIZE		64		/* flash size in MB */
#define CONFIG_SYS_FLASH_ADDR0		0x555
#define CONFIG_SYS_FLASH_ADDR1		0x2aa
#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short
#define CONFIG_SYS_FLASH_PORTWIDTH	2

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/* The following #defines are needed to get flash environment right */
#define	CONFIG_SYS_MONITOR_BASE	TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_INIT_SP_OFFSET	0x800000
#define CONFIG_SYS_PAGED_FLASH_PAGESIZE 0x00400000

#define CONFIG_8BIT_ROM

/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_PAGED_FLASH_END	1

/* Address and size of Primary Environment Sector	*/
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0xC0000)
#define CONFIG_ENV_SIZE			0x2000	/* Size of the Environment		*/
#define CONFIG_ENV_OFFSET		0	/* starting right at the beginning	*/
#define CONFIG_ENV_SECT_SIZE		0x20000 /* Size of the Environment Sector	*/

#define CONFIG_EPI3_LOCATION		(CONFIG_SYS_FLASH_BASE + 0xE0000)
#define CONFIG_EPI3_SIZE		0x20000

#define CONFIG_UBOOT_SIZE		0xC0000
#define CONFIG_UBOOT_FLASH_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_UBOOT_ROM_BASE		0x83000000 /* Not actually the ROM base on this product. See bootmenu code */

#define CONFIG_NVS_LOCATION		(CONFIG_SYS_FLASH_BASE + (CONFIG_SYS_FLASH_SIZE << 20))
#define CONFIG_NVS_SIZE			0x80000
#define CONFIG_DIAG_NVS_BYTE_OFFSET	0

#define CONFIG_NR_DRAM_BANKS	1

#define CONFIG_JFFS2_PART_OFFSET 0x00100000
#define CONFIG_JFFS2_PART_SIZE   (atl_get_jffs2_part_size())
#define DIAG_USER_FLASH_OFFSET		CONFIG_JFFS2_PART_OFFSET
#define DIAG_USER_FLASH_SIZE		CONFIG_JFFS2_PART_SIZE

/* Place to store a copy of the ROM image before the
 * user removed the access jumper (8MB boundry)
 */
#define CONFIG_ROMIMAGE_BASE    CONFIG_UBOOT_ROM_BASE
#define CONFIG_DIAGMEM_BASE     0x81000000

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_DCACHE_SIZE		32768
#define CONFIG_SYS_ICACHE_SIZE		32768
#define CONFIG_SYS_CACHELINE_SIZE	32

#endif	/* __CONFIG_H */
