/*
 * (C) Copyright 2010
 * Allied Telesis <www.alliedtelesis.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301 USA
 */

/* Based on include/configs/mv88f6281gtw_ge.h */

#ifndef _CONFIG_SBX81CFC_H
#define _CONFIG_SBX81CFC_H

/*
 * Version number information
 */
#define CONFIG_IDENT_STRING	"\nAT-SBx81CFC"

/*
 * High Level Configuration Options (easy to change)
 */
#define CONFIG_MARVELL		1
#define CONFIG_ARM926EJS	1	/* Basic Architecture */
#define CONFIG_SHEEVA_88SV571_VD 1	/* CPU Core subversion */
#define CONFIG_DISCOVERY	1	/* SOC Family Name */
#define CONFIG_MV78100		1	/* SOC Name */
#define CONFIG_MACH_SBX81CFC		/* Machine type */

#define CONFIG_MD5	/* get_random_hex on discovery needs MD5 support */
#define CONFIG_DISCOVERY_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
#define CONFIG_DISCOVERY_PCIE_INIT	/* Enable PCIE Ports for kernel */
#define CONFIG_DISCOVERY_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */

/*
 * Board level bootloader configuration
 */
#define CONFIG_SYS_USE_NOR
#undef CONFIG_SYS_USE_NAND
#undef CONFIG_SYS_USE_SPI

#if defined(CONFIG_SYS_USE_NOR) || defined(CONFIG_SYS_USE_NAND) || defined(CONFIG_SYS_USE_SPI)

#define CONFIG_SYS_BOOTROM_UBOOT_SIZE	0x000c0000 /* Limit U-Boot to last 0.75MiB of bootrom */

#if (CONFIG_SYS_BOOTROM_UBOOT_SIZE > (64*1024))
#define CONFIG_SYS_BOOTROM_UBOOT_LARGE
#endif

/* Address of TEXT_BASE in the bootrom */
#define CONFIG_SYS_BOOTROM_UBOOT_BASE	(0xffffffff - (CONFIG_SYS_BOOTROM_UBOOT_SIZE - 1))
/* Address of the ARM Reset exception */
#define CONFIG_SYS_BOOTROM_RESET_ADDR	0xffff0000

#define BOOTROM_ADDR_TO_PHY_ADDR(_b)	(TEXT_BASE + ((_b) - CONFIG_SYS_BOOTROM_UBOOT_BASE))
#define RESET_VECTOR_ADDRESS		BOOTROM_ADDR_TO_PHY_ADDR(CONFIG_SYS_BOOTROM_RESET_ADDR)

/* When loading U-Boot directly out of BootROM */
#undef CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot run from ROM, need to do init */
#undef CONFIG_SKIP_RELOCATE_UBOOT	/* and relocate to a proper address */

#else

/* When loading U-Boot from another bootloader */
#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
#define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init already done */

#endif

#define CONFIG_MISC_INIT_R		/* call misc_init_r */

/*
 * CLKs configurations
 */
#define CONFIG_SYS_HZ		1000

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
#define CONFIG_SYS_NS16550_COM1		DISCO_UART0_BASE

/*
 * RTC Configuration
 */
#define CONFIG_RTC_DS1340		/* Actual RTC on board */
#define CONFIG_RTC_DS1307		/* But this is good enough */

/*
 * Serial Port configuration
 * The following definitions let you select what serial you want to use
 * for your console driver.
 */

#define CONFIG_CONS_INDEX	1	/*Console on UART0 */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
#define CONFIG_INITRD_TAG	1	/* enable INITRD tag */
#define CONFIG_SETUP_MEMORY_TAGS 1	/* enable memory tag */

#define	CONFIG_SYS_PROMPT	"=> "	/* Command Prompt */

/*
 * Commands configuration
 */
#include <config_cmd_default.h>
#define CONFIG_CMD_AUTOSCRIPT
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
/*#define CONFIG_CMD_SF*/
#define CONFIG_CMD_USB

#define CONFIG_CMDLINE_EDITING

/*
 * Flash configuration
 */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */

#define CONFIG_HARD_SPI			1
#define CONFIG_DISCOVERY_SPI		1
#ifdef CONFIG_CMD_SF
#define CONFIG_SPI_FLASH		1
#define CONFIG_SPI_FLASH_MACRONIX	1
#endif

#define CONFIG_SYS_FLASH_BASE		0xf8000000	/* start of whole FLASH (2x64MiB) */
#define CONFIG_SYS_FLASH_SIZE		128		/* 128MiB Flash Max */
#define CONFIG_SYS_MAX_FLASH_BANKS	4		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	520		/* sectors per device */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ { 0xfff00000, 0x00100000 } }

#define CONFIG_NVS_LOCATION		0xf2080000
#define CONFIG_NVS_SIZE		0x00080000 /* 512K */

/*
 *  JFFS2 configuration
 */
#define CONFIG_JFFS2_PART_OFFSET	0x00000000	/* Used by JFFS2 */
#define CONFIG_JFFS2_PART_SIZE		0x07e00000	/* 126MiB */
#define DIAG_USER_FLASH_OFFSET		CONFIG_JFFS2_PART_OFFSET
#define DIAG_USER_FLASH_SIZE		(CONFIG_JFFS2_PART_SIZE + 0x00100000)	/* 127MiB (Includes errlog) */

#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:126M(user),1M(errlog),128K(epi3)ro,128K(boot-env),768K(boot)ro;mtd-ram:-(nvs)"
#define MTDPARTS_MTDOOPS "errlog"
#define CONFIG_MMC_SPI
#define CONFIG_DOS_PARTITION
#define CONFIG_MMC_MAX_FREQ		400000	/* 400Khz */

/*
 *  EPI3 configuration - these aren't used but give us a reserved sector
 *  that could be used later.
 */
#define CONFIG_EPI3_SIZE		0x00020000	/* 128KiB (1 Flash block) */
#define CONFIG_EPI3_LOCATION		0xfff00000

/*
 *  Environment variables configurations
 */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE		0x00020000	/* 128KiB (one sector) for env */
#define CONFIG_ENV_SIZE			0x00002000
#define CONFIG_ENV_ADDR			0xfff20000

/*
 * U-Boot bootcode configuration
 */
#define CONFIG_UBOOT_FLASH_BASE		0xfff40000
#define CONFIG_UBOOT_ROM_BASE		CONFIG_UBOOT_FLASH_BASE	/* Used only by the AW+ upgrader/installer */
#define CONFIG_UBOOT_SIZE		0x000c0000	/* 768KiB - Used only by the AW+ upgrader/installer & diagnostics */

/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE	128

/*
 * Other required minimal configurations
 */
/*#define CONFIG_CONSOLE_INFO_QUIET*/	/* some code reduction */
#define CONFIG_ARCH_CPU_INIT	/* call arch_cpu_init() */
#define CONFIG_ARCH_MISC_INIT	/* call arch_misc_init() */
#define CONFIG_DISPLAY_CPUINFO	/* Display cpu info */
#define CONFIG_NR_DRAM_BANKS	4
#define CONFIG_STACKSIZE	0x00100000	/* regular stack- 1M */
#define CONFIG_SYS_MEMTEST_START 0x00400000	/* 4M */
#define CONFIG_SYS_MEMTEST_END	0x007fffff	/*(_8M -1) */
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */

#ifdef CONFIG_CMD_NET

/*
 * Ethernet Driver configuration
 */
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_NETCONSOLE	/* include NetConsole support   */
#define CONFIG_NET_MULTI	/* specify more that one ports available */
#define	CONFIG_MII		/* expose smi over miiphy interface */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */

#define CONFIG_DISCOVERY_EGIGA	/* Enable discovery Gbe Controller Driver */
#define CONFIG_DISCOVERY_EGIGA_PORTS	{1,1}	/* enable both ports */
#define CONFIG_DISCOVERY_EGIGA_DEVNUM	{1,0}	/* swap egiga0/1 for SBx81CFC */
#define CONFIG_DISCOVERY_EGIGA_PHY_ADR	{0x10,0x01} /* Phy adr for port 0/1 */

#define CONFIG_ETHPRIME		"egiga0"

#define CONFIG_RGMII		/* Reduced-GMII PHY interface */

#define CONFIG_98DX160		1	/* Marvell 98dx160 */
#define CONFIG_98DX160_ADDR	0x10	/* Marvell 98dx160 SMI address */

/*
 * Marvell 88Exxxx Phy configurations
 */
#define CONFIG_RESET_PHY_R	/* use reset_phy() to init phy/swtich */
#define CONFIG_M88E1111_PHY

#endif /* CONFIG_CMD_NET */

/*
 * I2C related stuff
 */
#define CONFIG_HARD_I2C			/* I2C with hardware support */
#undef CONFIG_SOFT_I2C			/* I2C bit-banged       */
#define CONFIG_CMD_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_MUX
#define CONFIG_I2C_MUX_BUS 1
#define CONFIG_SYS_I2C_MUX_DESC	"pca9548:70:0x01:pca9548:71:0x00:pca9548:72:0x00", \
					"pca9548:70:0x02:pca9548:71:0x00:pca9548:72:0x00", \
					"pca9548:70:0x04:pca9548:71:0x00:pca9548:72:0x00", \
					"pca9548:70:0x00:pca9548:71:0x08:pca9548:72:0x00", \
					"pca9548:70:0x00:pca9548:71:0x00:pca9548:72:0x08", \
					"pca9548:70:0x00:pca9548:71:0x00:pca9548:72:0x10", \
					"pca9548:70:0x00:pca9548:71:0x00:pca9548:72:0x00"

#define CONFIG_I2C_BACKPLANE_BUS	1
#ifdef CONFIG_I2C_BACKPLANE_BUS
#define CONFIG_I2C_PSUA_BUS	2
#define CONFIG_I2C_PSUB_BUS	3
#define CONFIG_I2C_FANTRAY_BUS	4
#define CONFIG_I2C_PSUC_BUS	5
#define CONFIG_I2C_PSUD_BUS	6
#define CONFIG_I2C_CHASSIS_BUS	7
#endif

#if defined(CONFIG_HARD_I2C)
#define CONFIG_I2C_DISCOVERY
#define CONFIG_I2C_DISCO_REG_BASE	DISCO_TWSI0_BASE
#define CONFIG_SYS_I2C_SLAVE		0x0
#define CONFIG_SYS_I2C_SPEED		100000
#endif

#define CONFIG_MPI_GPIO			0x74
#define CONFIG_PCA953X			/* PCA953x GPIO driver */
#define CONFIG_SYS_I2C_PCA953X_WIDTH	{{CONFIG_MPI_GPIO, 16}}
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO

/*
 * USB/EHCI
 */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI			/* Enable EHCI USB support */
#define CONFIG_USB_EHCI_DISCOVERY	/* on Discovery platform	*/
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
/*#define CONFIG_ISO_PARTITION*/
#define CONFIG_SUPPORT_VFAT
#endif /* CONFIG_CMD_USB */

/*********************************************************************
 * ATL specific extensions
 *********************************************************************/

#define CONFIG_THIS_DEVICE		3
#define CONFIG_RELEASE_SPECIAL		1
#define CONFIG_COMPATIBLE_DEVICES	\
{					\
	{ 316, "AT-SBx81CFC" },		\
	{ 0, NULL }			\
}

#define CONFIG_BOOTMENU
#define CONFIG_DIAGNOSTICS
#define CONFIG_DIAG_USB
#define CONFIG_DIAG_NOR_FLASH
#define CONFIG_DIAG_RAM_START 0
#define CONFIG_DIAG_RAM_SKIP_SIZE 0x00800000 /* skip first 8MB for code */
#define CONFIG_DIAG_IDPROM
#define CONFIG_IDPROM_LOCAL_ADDR	0x52
#define CONFIG_IDPROM_BACKPLANE_ADDR	0x50
#define CONFIG_DIAGMEM_BASE		0x01000000

#define CONFIG_BOARD_EXTRA_ENV_SETTINGS	\
	"ethprime="CONFIG_ETHPRIME"\0"

#include <configs/atl-std-opts.h>
#undef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
/* TODO: enable these in future images */
#undef CONFIG_CMD_PCI
/* #undef CONFIG_CMD_DATE */

/* This board does not user the DS1302, it uses DS1340/DS1307 instead */
#undef CONFIG_RTC_DS1302_ATL

#endif /* _CONFIG_SBX81CFC_H */
