/*
 * Copyright 2008-2009 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * mpc8536ds board configuration file
 *
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_X610
#define CONFIG_DIAGNOSTICS
#define CONFIG_DIAG_NOR_FLASH
#define CONFIG_DIAG_EPI3
#define CONFIG_DIAG_EPI3_PSU
#define CONFIG_MAX_PSU 1
#define CONFIG_BOOTMENU
#define CONFIG_SYS_STDALONE_TFTP

#define CONFIG_COMPATIBLE_DEVICES       \
{                                       \
	{ 330, "x610-48Ts/X-POE+" },	\
	{ 331, "x610-48Ts-POE+" },	\
	{ 332, "x610-24Ts/X-POE+" },	\
	{ 333, "x610-24Ts-POE+" },	\
	{ 338, "x610-48Ts/X" },		\
	{ 339, "x610-48Ts" },		\
	{ 340, "x610-24Ts/X" },		\
	{ 341, "x610-24Ts" },		\
	{ 342, "x610-24SPs/X" },	\
	{ 0, NULL }			\
}
#define CONFIG_THIS_DEVICE  7

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
#define CONFIG_MPC8536		1
#define CONFIG_MPC8536DS	1

#define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
#define CONFIG_PCI		1	/* Enable PCI/PCIE */
#define CONFIG_PCI1		1	/* Enable PCI controller 1 */
#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */

#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
#define CONFIG_E1000		1	/* Defind e1000 pci Ethernet card*/

#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_ETH_SWITCH		/* Boot from switch ports */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_SYS_CLK_FREQ	66666000            /* 66.666 MHz */
#define CONFIG_DDR_CLK_FREQ	CONFIG_SYS_CLK_FREQ /* SYS_CLK and DDR_CLK use the same source */

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */

#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
#define CONFIG_MISC_INIT_R		1	/* Call misc_init_f */

#define CONFIG_ENABLE_36BIT_PHYS	1

#define CONFIG_SYS_MEMTEST_START 0x00010000	/* skip exception vectors */
#define CONFIG_SYS_MEMTEST_END   0x1f000000	/* skip u-boot at top of RAM */

/*
 * Config the L2 Cache as L2 SRAM
 */
#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8f80000ull
#else
#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
#endif
#define CONFIG_SYS_L2_SIZE		(512 << 10)
#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_CCSRBAR_PHYS	0xfffe00000ull /* physical addr of CCSRBAR */
#else
#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR
#endif
#define CONFIG_SYS_IMMR	CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */

#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */

#define CONFIG_SYS_PCI1_ADDR		(CONFIG_SYS_CCSRBAR + 0x8000)
#define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR + 0xa000)
#define CONFIG_SYS_PCIE2_ADDR		(CONFIG_SYS_CCSRBAR + 0x9000)
#define CONFIG_SYS_PCIE3_ADDR		(CONFIG_SYS_CCSRBAR + 0xb000)

/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
// #define CONFIG_FSL_DDR2
// #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
// #define CONFIG_DDR_SPD

#define CONFIG_MEM_INIT_VALUE	0xdeadbeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	2

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
#define CONFIG_SYS_SPD_BUS_NUM		1

#ifndef CONFIG_SPD_EEPROM
/* These are used when DDR doesn't use SPD. */

/* The RAM device is a Samsung K4B1G1646E-HCF8 which uses 64Mx16 organisation
 * giving us 13 rows 10 cols 3 banks with a 2K page size.
 * The DDR clock is 333MHz which gives us tCK = 3ns.
 */
#define CONFIG_DDR_ECC			1
#define CONFIG_SYS_SDRAM_SIZE		512	/* DDR is 512MB */
#define CONFIG_SYS_DDR_CS2_BNDS		0x0000001f
#define CONFIG_SYS_DDR_CS2_CONFIG	0x80014102 /* Enable, no interleaving */
#define CONFIG_SYS_DDR_CS2_CONFIG_2	0x00000000
#define CONFIG_SYS_DDR_TIMING_3		0x00010000
#define CONFIG_SYS_DDR_TIMING_0		0x00330A04
#define CONFIG_SYS_DDR_TIMING_1		0x5D5BD746
#define CONFIG_SYS_DDR_TIMING_2		0x0FA8D0D1
#define CONFIG_SYS_DDR_SDRAM_CFG	0x47000000 /* Type = DDR3. ECC is enabled base on CONFIG_DDR_ECC */
#define CONFIG_SYS_DDR_SDRAM_CFG_2	0x24401050
#define CONFIG_SYS_DDR_MODE_1		0x40060221
#define CONFIG_SYS_DDR_MODE_2		0x8000C000
#define CONFIG_SYS_DDR_INTERVAL		0x05140100
#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
#define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
#define CONFIG_SYS_DDR_TIMING_4		0x00440001
#define CONFIG_SYS_DDR_TIMING_5		0x00002400
#define CONFIG_SYS_DDR_ZQ_CNTL		0x89080600
#define CONFIG_SYS_DDR_WRLVL_CNTL	0x86559605

#define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
#define CONFIG_SYS_DDR_SBE		0x00010000
#endif /* CONFIG_SPD_EEPROM */

/*
 * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
 * 0x8000_0000	0xbfff_ffff	PCI			1G non-cacheable
 * 0xe000_0000	0xe3ff_ffff	PCI IO range		64M non-cacheable
 *
 * Localbus non-cacheable
 * 0xe800_0000	0xefff_ffff	FLASH			128M
 * 0xffa0_0000	0xffaf_ffff	NVS			1M
 * 0xffdf_0000	0xffdf_7fff	CPLD			32K
 * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
 * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
 */

/*
 * Local Bus Definitions
 */
#define CONFIG_SYS_FLASH_BASE		0xec000000	/* start of FLASH */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
#else
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
#endif
#define CONFIG_FLASH_SIZE		0x02000000 /* Our chips represent themselves as 2x32MB */

#define CONFIG_SYS_CPLD_BASE		0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS	CONFIG_SYS_CPLD_BASE
#define CONFIG_NVS_LOCATION		0xffa00000
#define CONFIG_NVS_LOCATION_PHYS	CONFIG_NVS_LOCATION
#define CONFIG_NVS_SIZE		0x80000


#define CONFIG_JFFS2_PART_OFFSET 0x0
#define CONFIG_JFFS2_PART_SIZE atl_get_jffs2_part_size()
#define DIAG_USER_FLASH_OFFSET		CONFIG_JFFS2_PART_OFFSET
#define DIAG_USER_FLASH_SIZE		CONFIG_JFFS2_PART_SIZE


#define CONFIG_FLASH_BR_PRELIM \
		(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
		 | BR_PS_16 | BR_V)
#define CONFIG_FLASH_OR_PRELIM	\
		(OR_AM_128MB | \
		 OR_GPCM_CSNT | \
		 OR_GPCM_ACS_DIV2 | \
		 OR_GPCM_SCY_3)

#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE_PHYS+CONFIG_FLASH_SIZE }
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	2
#ifndef __ASSEMBLY__
extern int cfi_flash_num_flash_banks;
#endif
#define CONFIG_SYS_MAX_FLASH_BANKS (cfi_flash_num_flash_banks)
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE

#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
#define CONFIG_SYS_STDALONE_APP_SIZE	0x40000
#define CONFIG_UBOOT_FLASH_BASE 	(TEXT_BASE - CONFIG_SYS_STDALONE_APP_SIZE)
#define CONFIG_UBOOT_SIZE 		(0x80000 + CONFIG_SYS_STDALONE_APP_SIZE)
#define CONFIG_UBOOT_ROM_BASE 		(0xeff80000 - CONFIG_SYS_STDALONE_APP_SIZE)

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7

#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */

#define CONFIG_SYS_BR3_PRELIM	0
#define CONFIG_SYS_OR3_PRELIM	0

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in RAM */

#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET \
		(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM	/* NOR Options */

#define CONFIG_SYS_BR1_PRELIM	(BR_PHYS_ADDR((CONFIG_SYS_CPLD_BASE_PHYS)) \
				 | BR_PS_8 | BR_V)
#define CONFIG_SYS_OR1_PRELIM	(OR_AM_32KB | OR_GPCM_CSNT \
				 | OR_GPCM_XACS \
				 | OR_GPCM_SCY_15 | OR_GPCM_TRLX \
				 | OR_GPCM_EHTR | OR_GPCM_EAD)

#define CONFIG_SYS_BR2_PRELIM  (BR_PHYS_ADDR((CONFIG_NVS_LOCATION_PHYS)) \
				 | BR_PS_8 | BR_V)
#define CONFIG_SYS_OR2_PRELIM	(OR_AM_512KB | OR_GPCM_SCY_4)


#define CONFIG_SYS_BR4_PRELIM 0
#define CONFIG_SYS_OR4_PRELIM 0
#define CONFIG_SYS_BR5_PRELIM 0
#define CONFIG_SYS_OR5_PRELIM 0

#define CONFIG_SYS_BR6_PRELIM 0
#define CONFIG_SYS_OR6_PRELIM 0

/* Serial Port - controlled on board with jumper J8
 * open - index 2
 * shorted - index 1
 */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef	CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif

/*
 * Pass open firmware flat tree
 */
#define CONFIG_OF_LIBFDT		1
#define CONFIG_OF_BOARD_SETUP		1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/*
 * I2C
 */
#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
#define CONFIG_HARD_I2C		/* I2C with hardware support */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_NOPROBES	{{0}}	/* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET		0x3000
#define CONFIG_SYS_I2C2_OFFSET		0x3100
#define CONFIG_I2C_MUX			1
#define CONFIG_SYS_I2C_MUX_DESC	"pca9554a:70:4", \
					"pca9554a:70:5", \
					"pca9554a:70:6", \
					"pca9554a:70:7"

/*
 * I2C2 EEPROM
 */
#define CONFIG_ID_EEPROM
#ifdef CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#endif
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_EEPROM_BUS_NUM	1

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */

#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCI1_MEM_BUS		0xf0000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0xc00000000ull
#else
#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
#endif
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT		0xe0000000
#define CONFIG_SYS_PCI1_IO_BUS		0xe0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCI1_IO_PHYS		0xfffc00000ull
#else
#define CONFIG_SYS_PCI1_IO_PHYS		0xe0000000
#endif
#define CONFIG_SYS_PCI1_IO_SIZE		0x04000000	/* 64M */

#if defined(CONFIG_PCI)

#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP			/* do pci plug-and-play */

#ifndef CONFIG_PCI_PNP
	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BUS
	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_IO_BUS
	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
#endif

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */

#endif	/* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI	1
#endif

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"eTSEC1"
#define TSEC1_PHY_ADDR		0x21	/* TSEC1 -> PHY1 */

#define TSEC1_FLAGS		TSEC_GIGABIT

#define TSEC1_PHYIDX		0

#define CONFIG_ETHPRIME		"eTSEC1"

#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */

#endif	/* CONFIG_TSEC_ENET */

/* GPIO setup */
#define CONFIG_SYS_GPDIR_VAL	0x00EB0000
#define CONFIG_SYS_GPODR_VAL	0x00000000
#define CONFIG_SYS_GPIMR_VAL	0xFF040000
#define CONFIG_SYS_GPICR_VAL	0x00000000

/* GPIO output pin initial states are
 * 1. Fault LED off (GPIO 10, 1=off)
 * 2. Both Master LEDs off (GPIOS 8 & 9, 1=off)
 * 3. POE held in reset (GPIO 12, 0=reset)
 * 4. EEPROM write protect on (GPIO 14, 1=protect)
 * 5. Stack module in reset (GPIO 15, 0=reset)
 */
#define CONFIG_SYS_GPDAT_INIT_VAL	0x00E20000

/*
 * Environment
 */

#if defined(CONFIG_SYS_RAMBOOT)
	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
	#define CONFIG_ENV_SIZE		0x2000
#else
	#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
	#define CONFIG_ENV_ADDR		0xfff80000
	#else
	#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - (CONFIG_ENV_SECT_SIZE + CONFIG_SYS_STDALONE_APP_SIZE))
	#endif
	#define CONFIG_ENV_SIZE		0x2000
	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

#define CONFIG_RTC_DS1338
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_RTC_BUS_NUM  2

#define CONFIG_THIS_DEVICE 7
#define CONFIG_DIAGMEM_BASE  0x1000000
#define CONFIG_EPI3_LOCATION (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
#define CONFIG_EPI3_SIZE CONFIG_ENV_SECT_SIZE

#include <configs/atl-std-opts.h>
// #undef CONFIG_SILENT_CONSOLE

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>
// undefine some of the defaults we don't want
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_XIMG

#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR

#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#define CONFIG_CMD_NET
#endif

#define CONFIG_MMC_SPI
#define CONFIG_ESPI
#define CONFIG_ESPI_CS		0
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#define CONFIG_MMC_MAX_FREQ	20000000

/* Support lzma decompression */
#define CONFIG_LZMA

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#endif

#define CONFIG_HOSTNAME		unknown
#define CONFIG_ROOTPATH		/opt/nfsroot
#define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */

#endif	/* __CONFIG_H */
