/*
 * atrdx300.h
 * Matthew Millman
 */
 
#ifndef __CONFIG_H
#define __CONFIG_H

/* Below is a brief description of what is where in memory while uboot is running
 * on our MIPS environment
 *
 *	All addresses are from the kseg0 view of RAM
 *
 *	0x80001000-0x806FFFFF (~7MB)
 *	Linux kernel binary is loaded into this address
 *	by the boot_alliedware_package function from the DIAGMEM load point.
 *	The linux kernel is typically only about 3MB therefore doesn't use all
 *	of this space.
 *	0x80800000-0x80FFFFFF (8MB)
 *	C Code in uboot has it's stack in this location
 *	The kernel command line and bd_t struct are loaded just before this location
 *	when the kernel is kicked off.
 *	0x81000000-0x82FFFFFF (32MB)
 *	DIAGMEM location. This is use for a number of tasks where some data needs to be
 *	temporarily stored. i.e. when a package is TFTP downloaded, it gets stored here
 *	0x83000000-0x83080000 (512KB)
 *	A temporary copy of the boot rom is stored here for loading from boot rom to flash
 *	Hopefully this should be able to removed in the future
 *
 *	These boundaries are guidelines and are not enforced by *anything* at present.
 */

#define CONFIG_MIPS32		1	/* MIPS 4Kc CPU core	*/
#define CONFIG_ATRD_X300	1	/* on a x300 Board	*/

#define CONFIG_THIS_DEVICE 3 
#define CONFIG_COMPATIBLE_DEVICES 	\
{ 					\
	{ 303, "x300-24Ts" },		\
	{ 0, NULL }			\
}

#define CONFIG_DIAGNOSTICS
#define CONFIG_DIAG_EPI3
#define CONFIG_BOOTMENU
#define CONFIG_SYS_STDALONE_TFTP

/* Serial Port */
#define CONFIG_CONS_INDEX     1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE    1
#define CFG_NS16550_CLK		(x300_get_cpuclk() / 2)

#define CFG_NS16550_COM1        (0xB8000300)
#define CFG_NS16550_COM2        (0xB8000400)

#define CONFIG_BAUDRATE		9600

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */

#include <configs/atl-std-opts.h>

#define CONFIG_COMMANDS         (CONFIG_GENERIC_COMMANDS | CFG_CMD_I2C)

#include <cmd_confdefs.h>
/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP				/* undef to save memory      */
#define	CFG_PROMPT		"x300> "	/* Monitor Command Prompt    */
#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */

#define CFG_BOOTPARAMS_LEN	128*1024

#undef CFG_HZ
#define CFG_HZ			(x300_get_cpuclk() / 2)

#define CFG_SDRAM_BASE		0x80000000

#define CFG_MEMTEST_START	0x00100000
#define CFG_MEMTEST_END		0x00800000

#define CONFIG_MISC_INIT_R

#define CONFIG_ETH_SWITCH		/* Boot from switch ports */
#define CONFIG_NET_MULTI		/* Multi ethernet cards support */

/*
 * I2C
 */
 
#define CONFIG_RTC_MAX6900
#define CONFIG_HARD_I2C			/* I2C with hardware support*/
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CFG_FLASH_CFI
#define CFG_FLASH_USE_BUFFER_WRITE
#define CFG_FLASH_PROTECTION

#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */

#define PHYS_FLASH_1		0xBC000000 /* Flash Bank #1 */

/* The following #defines are needed to get flash environment right */
#define	CFG_MONITOR_BASE	TEXT_BASE

#define CFG_INIT_SP_OFFSET	0x800000

#define CFG_FLASH_BASE		PHYS_FLASH_1

#define CONFIG_FLASH_8BIT
#define CONFIG_8BIT_ROM


/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/* Address and size of Primary Environment Sector	*/
#define CFG_ENV_ADDR		0xBC0C0000
#define CFG_ENV_SIZE		0x2000	/* Size of the Environment		*/
#define CFG_ENV_OFFSET		0	/* starting right at the beginning	*/
#define CFG_ENV_SECT_SIZE	0x20000 /* Size of the Environment Sector	*/

#define CONFIG_EPI3_LOCATION    0xBC0E0000
#define CONFIG_EPI3_SIZE        0x20000

#define CONFIG_UBOOT_SIZE 	0xC0000
#define CONFIG_UBOOT_FLASH_BASE 0xBC000000
#define CONFIG_UBOOT_ROM_BASE   0x83000000 /* Not actually the ROM base on this product. See bootmenu code */

#define CONFIG_NVS_LOCATION	0xBE000000
#define CONFIG_NVS_SIZE		0x80000

#define CONFIG_NR_DRAM_BANKS	1

#define CONFIG_JFFS2_PART_OFFSET 0x100000
#define CONFIG_JFFS2_PART_SIZE  0xF00000

/* Place to store a copy of the ROM image before the
 * user removed the access jumper (8MB boundry)
 */
#define CONFIG_ROMIMAGE_BASE    CONFIG_UBOOT_ROM_BASE
#define CONFIG_DIAGMEM_BASE     0x81000000

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		32768
#define CFG_ICACHE_SIZE		32768
#define CFG_CACHELINE_SIZE	16

/*
 *  memory configuration
 */

#define CONFIG_MEMDDR
#define CONFIG_DDRM32X16X1
#define CONFIG_SDRM64X16X1


#endif	/* __CONFIG_H */
