/*
 * Copyright (C) 2009 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * Rapier48x board configuration file
 */
#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE			1	/* BOOKE */
#define CONFIG_E500			1	/* BOOKE e500 family */
#define CONFIG_MPC85xx			1	/* MPC8540/60/55/41/48/68 */
#define CONFIG_MPC8569			1	/* MPC8569 specific */
#define CONFIG_RAPIER48x		1	/* RAPIER48x board specific */
#define CONFIG_DIAGNOSTICS
#define CONFIG_DIAG_NOR_FLASH
#define CONFIG_DIAG_EPI3
#define CONFIG_DIAGNOSTICS_SPLASH_RAPTOR
#define CONFIG_BOOTMENU
#define CONFIG_SYS_STDALONE_TFTP
#define CONFIG_COMPATIBLE_DEVICES       \
{                                       \
	{ 344, "rapier48x" },	\
	{ 0, NULL }			\
}
#define CONFIG_THIS_DEVICE		4	/* R4 = Rapier48x */
#define CONFIG_FIT			1	/* Support for new Device Tree uImage format */

#define CONFIG_FSL_ELBC			1	/* Has Enhance localbus controller */

#define CONFIG_PCI			1	/* Disable PCI/PCIE */
#define CONFIG_PCIE1			1	/* PCIE controller */
#define CONFIG_FSL_PCI_INIT		1	/* use common fsl pci init code */
#define CONFIG_FSL_PCIE_RESET		1	/* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT		1	/* enable 64-bit PCI resources */
#define CONFIG_QE				/* Enable QE */
#define CONFIG_ETH_SWITCH			/* Boot from switch ports */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW			1	/* Use common FSL init code */

#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq (void);
#endif
/* Replace a call to get_clock_freq (after it is implemented)*/
#define CONFIG_SYS_CLK_FREQ		100000000
#define CONFIG_DDR_CLK_FREQ		CONFIG_SYS_CLK_FREQ

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache      */
#define CONFIG_BTB			/* toggle branch predition */

/*
 * Only possible on E500 Version 2 or newer cores.
 */
#define CONFIG_ENABLE_36BIT_PHYS	1

#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_R		/* Call board_early_init_r */
#define CONFIG_MISC_INIT_R		1	/* Call misc_init_f */
#define CONFIG_HWCONFIG

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00400000

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CONFIG_SYS_CCSRBAR		0xfb000000	/* relocated CCSRBAR */
#define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
#define CONFIG_SYS_IMMR			CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */

#define CONFIG_SYS_QE_BASE		(CONFIG_SYS_CCSRBAR+0x80000)
#define CONFIG_SYS_QE_DPRAM_BASE	(CONFIG_SYS_QE_BASE+0x10000)
#define CONFIG_SYS_QE_DPRAM_SIZE	0x20000
#define CONFIG_SYS_QE_IRAM_BASE		(CONFIG_SYS_QE_BASE+0x7000)
#define CONFIG_SYS_QE_IRAM_SIZE		0x40000

#define CONFIG_SYS_PCI1_ADDR		(CONFIG_SYS_CCSRBAR+0x8000)
#define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR+0xa000)

/* DDR Setup */
#define CONFIG_FSL_DDR3
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_DDR_DLL			/* possible DLL fix needed */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

/* 600Mhz */
#define CONFIG_DDR_ECC			1
#define CONFIG_SYS_SDRAM_SIZE           512	/* DDR is 512MB */
#define CONFIG_SYS_DDR_CS2_BNDS         0x0000001F
#define CONFIG_SYS_DDR_CS2_CONFIG       0x80014102
#define CONFIG_SYS_DDR_TIMING_3         0x00010000
#define CONFIG_SYS_DDR_TIMING_0         0x00330A04
#define CONFIG_SYS_DDR_TIMING_1         0x4C49A746
#define CONFIG_SYS_DDR_TIMING_2         0x0FA8D0D0
#define CONFIG_SYS_DDR_SDRAM_CFG	0x47000000
#define CONFIG_SYS_DDR_SDRAM_CFG_2	0x24401050
#define CONFIG_SYS_DDR_SDRAM_MODE	0x40440211
#define CONFIG_SYS_DDR_SDRAM_MODE_2	0x8000C000
#define CONFIG_SYS_DDR_SDRAM_INTERVAL	0x04930100
#define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x02000000
#define CONFIG_SYS_DDR_TIMING_4         0x00440001
#define CONFIG_SYS_DDR_TIMING_5         0x03002400
#define CONFIG_SYS_DDR_ZQ_CNTL		0x89080600
#define CONFIG_SYS_DDR_WRLVL_CNTL	0x8675F508
#define CONFIG_SYS_DDR_CDR_1		0x00000000
#define CONFIG_SYS_DDR_CDR_2		0x00000000
#define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
#define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
#define CONFIG_SYS_DDR_CONTROL          0xC7000000	/* Type = DDR3 */

#define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
#define CONFIG_SYS_DDR_SBE		0x00010000

#undef CONFIG_CLOCKS_IN_MHZ

/*
 * Localbus non-cacheable
 * 0xf900_0000	0xf9ff_ffff	PLD (CS2) - 16MB
 * 0xfa00_0000	0xfa07_ffff	NVSRAM (CS1) - 512KB
 * 0xfb00_0000	0xfb0f_ffff	CCSR - 1M non-cacheable
 * 0xfc00_0000	0xffff_ffff	FLASH (CS0) - 64MB 
 */
/* Chip select 0 - Flash */
#define CONFIG_SYS_FLASH_BASE		0xfc000000
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
#define CONFIG_FLASH_SIZE		0x4000000
#define CONFIG_SYS_BR0_PRELIM		(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
		 			 | BR_PS_16 | BR_V)
#define CONFIG_SYS_OR0_PRELIM		(OR_AM_64MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 \
		 			 | OR_GPCM_SCY_3)

/* Chip select 1 - NVS */
#define CONFIG_NVS_LOCATION		0xfa000000
#define CONFIG_NVS_LOCATION_PHYS	CONFIG_NVS_LOCATION
#define CONFIG_NVS_SIZE			0x80000
#define CONFIG_SYS_BR1_PRELIM  		(BR_PHYS_ADDR((CONFIG_NVS_LOCATION_PHYS)) \
					 | BR_PS_8 | BR_V)
#define CONFIG_SYS_OR1_PRELIM		(OR_AM_512KB | OR_GPCM_SCY_4)

/* Chip select 2 - CPLD */
#define CONFIG_SYS_CPLD_BASE		0xe0000000
#define CONFIG_SYS_CPLD_PIC1_BASE	(CONFIG_SYS_CPLD_BASE+0x08000000)
#define CONFIG_SYS_CPLD_PIC2_BASE	(CONFIG_SYS_CPLD_BASE+0x08000200)
#define CONFIG_SYS_CPLD_PIC3_BASE	(CONFIG_SYS_CPLD_BASE+0x08000400)
#define CONFIG_SYS_CPLD_PIC4_BASE	(CONFIG_SYS_CPLD_BASE+0x08000600)
#define CONFIG_SYS_CPLD_REG_BASE	(CONFIG_SYS_CPLD_BASE+0x08001000)
#define CONFIG_SYS_CPLD_BASE_PHYS	CONFIG_SYS_CPLD_BASE
#define CONFIG_SYS_BR2_PRELIM		(BR_PHYS_ADDR((CONFIG_SYS_CPLD_BASE_PHYS)) \
				 	 | BR_PS_8 | BR_V)
#define CONFIG_SYS_OR2_PRELIM		(OR_AM_256MB | OR_GPCM_CSNT \
				 	 | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
				 	 | OR_GPCM_SCY_15 | OR_GPCM_TRLX \
				 	 | OR_GPCM_EHTR | OR_GPCM_EAD)

/* Flash - 64MB
 * 0xfc00_0000	0xffeb_ffff	“jffs”	 ~63M
 * 0xffec_0000	0xffed_ffff	“epi3”	128K
 * 0xffee_0000	0xffef_ffff	“u-boot-env”	128K
 * 0xfff0_0000	0xffff_ffff	“U-Boot (including tftp.bin & microcode)”	1M 
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { { CONFIG_UBOOT_FLASH_BASE, CONFIG_UBOOT_SIZE }, \
					    { CONFIG_EPI3_LOCATION_BASE, CONFIG_EPI3_SIZE }, \
					    { CONFIG_ENV_ADDR, CONFIG_ENV_SIZE} }

/* JFFS2 */
#define CONFIG_JFFS2_PART_OFFSET	0x0
#define CONFIG_JFFS2_PART_SIZE		atl_get_jffs2_part_size()
#define CONFIG_JFFS2_PART_SIZE_BASE	(CONFIG_EPI3_LOCATION_BASE - CONFIG_SYS_FLASH_BASE)
#define DIAG_USER_FLASH_OFFSET		CONFIG_JFFS2_PART_OFFSET
#define DIAG_USER_FLASH_SIZE		CONFIG_JFFS2_PART_SIZE

/* EPI3 */
#define CONFIG_EPI3_SIZE		0x20000
#define CONFIG_EPI3_LOCATION		atl_get_epi3_location()
#define CONFIG_EPI3_LOCATION_BASE	(CONFIG_ENV_ADDR - CONFIG_EPI3_SIZE)
#define CONFIG_DIAGMEM_BASE		0x01000000	/* Location in memory for use by diagnostics */

/* Environment */
#define CONFIG_ENV_ADDR			(CONFIG_UBOOT_FLASH_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K(one sector) for env */
#define CONFIG_ENV_SIZE			0x2000

/* U-boot */
#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE	/* start of monitor */
#ifdef CONFIG_SYS_STDALONE_TFTP
#define CONFIG_SYS_STDALONE_APP_SIZE	0x40000
#define CONFIG_SYS_STDALONE_RAM_ADDR	0x40000
#define CONFIG_SYS_STDALONE_FLASH_ADDR	(CONFIG_SYS_MONITOR_BASE - 0x40000)
#else
#define CONFIG_SYS_STDALONE_APP_SIZE	0
#endif
#ifdef CONFIG_QE
#define CONFIG_SYS_QE_FW_SIZE		0x40000
#define CONFIG_SYS_QE_FW_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_STDALONE_APP_SIZE - \
					 CONFIG_SYS_QE_FW_SIZE)
#else
#define CONFIG_SYS_QE_FW_SIZE		0
#endif
#define CONFIG_UBOOT_FLASH_BASE 	(TEXT_BASE - CONFIG_SYS_STDALONE_APP_SIZE - CONFIG_SYS_QE_FW_SIZE)
#define CONFIG_UBOOT_SIZE 		(0x80000 + CONFIG_SYS_STDALONE_APP_SIZE + CONFIG_SYS_QE_FW_SIZE)
#define CONFIG_UBOOT_ROM_BASE   	CONFIG_UBOOT_FLASH_BASE

#undef CONFIG_SYS_RAMBOOT

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO

#define CONFIG_SYS_LBC_LCRR		0x00000004	/* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR		0x00040000	/* LB config reg */
#define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xb0000000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END		0x4000	/* End of used area in RAM */

#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/* Serial Port */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SERIAL_MULTI		1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_NS16550_COM1		(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2		(CONFIG_SYS_CCSRBAR+0x4600)

/* Use the HUSH parser*/
#define CONFIG_SYS_HUSH_PARSER
#ifdef  CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT		1
#define CONFIG_OF_BOARD_SETUP		1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/*
 * I2C
 */
#define CONFIG_FSL_I2C			/* Use FSL common I2C driver */
#define CONFIG_HARD_I2C			/* I2C with hardware support */
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address - limited by DS1340 */
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_NOPROBES		{{0}}	/* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET		0x3000
#define CONFIG_SYS_I2C2_OFFSET		0x3100
#define CONFIG_I2C_MUX			1
#define CONFIG_SYS_I2C_MUX_DESC		"pca9544d:70:4", \
					"pca9544d:70:5", \
					"pca9544d:70:6", \
					"pca9544d:70:7"

/*
 * Config on-board RTC
 */
#define CONFIG_RTC_DS1340		/* Actual RTC on board */
#define CONFIG_RTC_DS1307		/* But this is good enough */
#define CONFIG_SYS_I2C_RTC_ADDR		0x68
#define CONFIG_SYS_RTC_BUS_NUM		4

/*
 * General PCI
 * Memory Addresses are mapped 1-1. I/O is mapped from 0
 */
#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xa0000000
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xa0000000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */

#define CONFIG_SYS_SRIO_MEM_VIRT	0xc0000000
#define CONFIG_SYS_SRIO_MEM_BUS		0xc0000000
#define CONFIG_SYS_SRIO_MEM_PHYS	0xc0000000

#if defined(CONFIG_PCI)

#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP			/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */

#endif /* CONFIG_PCI */

#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI		1
#endif

/*
 * Environment
 */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_W1

#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#define CONFIG_CMD_NET
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */

#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
						/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		32	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
						/* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1ms ticks */

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD			0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM			0x02	/* Software reboot */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE		230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX		2	/* which serial port to use */
#endif

/*
 * Environment Configuration
 */

/* Include ATL generic settings  */
#include <configs/atl-std-opts.h>

#endif /* __CONFIG_H */
