/*
 * x210_atrd.h
 * Graeme Campbell
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* Below is a brief description of what is where in memory while uboot is running
 * on our MIPS environment
 *
 *	All addresses are from the kseg0 view of RAM
 *
 *	0x80001000-0x806FFFFF (~7MB)
 *	Linux kernel binary is loaded into this address
 *	by the boot_alliedware_package function from the DIAGMEM load point.
 *	The linux kernel is typically only about 3MB therefore doesn't use all
 *	of this space.
 *	0x80800000-0x80FFFFFF (8MB)
 *	C Code in uboot has it's stack in this location
 *	The kernel command line and bd_t struct are loaded just before this location
 *	when the kernel is kicked off.
 *	0x81000000-0x82FFFFFF (32MB)
 *	DIAGMEM location. This is use for a number of tasks where some data needs to be
 *	temporarily stored. i.e. when a package is TFTP downloaded, it gets stored here
 *	0x83000000-0x83080000 (512KB)
 *	A temporary copy of the boot rom is stored here for loading from boot rom to flash
 *	Hopefully this should be able to removed in the future
 *
 *	These boundaries are guidelines and are not enforced by *anything* at present.
 */

#define CONFIG_MIPS32		1	/* MIPS 4Kc CPU core	*/
#define CONFIG_X210_ATRD		1	/* on a x210 boards designed by ATRD */
#define CONFIG_DIAGNOSTICS
#define CONFIG_DIAG_NOR_FLASH
#define CONFIG_DIAG_EPI3
#define CONFIG_BOOTMENU
#define CONFIG_SYS_STDALONE_TFTP

#define CONFIG_THIS_DEVICE 8
#define CONFIG_COMPATIBLE_DEVICES 	\
{ 					\
	{ 366, "x210-9GT" },	\
	{ 367, "x210-16GT" },	\
	{ 368, "x210-24GT" },	\
	{ 0, NULL }			\
}


/* Serial Port */
#define CONFIG_CONS_INDEX     1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE    1
#define CONFIG_SYS_NS16550_CLK		x210_atrd_serial_base_clock()

#define CONFIG_SYS_NS16550_COM1        (0xB8000300)
#define CONFIG_SYS_NS16550_COM2        (0xB8000400)

#define CONFIG_BAUDRATE		9600

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */

#include <configs/atl-std-opts.h>
#undef CONFIG_CMD_DATE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_MII

#include <config_cmd_default.h>
/*
 * Miscellaneous configurable options
 */
#define CONFIG_ENV_OVERWRITE
#define	CONFIG_SYS_LONGHELP				/* undef to save memory      */
#define	CONFIG_SYS_PROMPT		"x210> "	/* Monitor Command Prompt    */
#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size   */
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */

#define CONFIG_SYS_INIT_RAM_LOCK_MIPS    1

#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024

#undef CONFIG_SYS_HZ
#define CONFIG_SYS_HZ			1000
#define CONFIG_SYS_MIPS_TIMER_FREQ	x210_atrd_system_counter_freq()

#define CONFIG_SYS_SDRAM_BASE		0x80000000
#define CONFIG_DIAG_RAM_START		CONFIG_SYS_SDRAM_BASE
#define CONFIG_DIAG_RAM_SKIP_SIZE	0x00800000

#define CONFIG_SYS_MEMTEST_START	0x00200000
#define CONFIG_SYS_MEMTEST_END		0x00800000

#define CONFIG_MISC_INIT_R

#define CONFIG_ETH_SWITCH		/* Boot from switch ports */
#define CONFIG_NET_MULTI		/* Multi ethernet cards support */

#define CONFIG_LZMA		1
/*
 * I2C
 */
#define CONFIG_HARD_I2C			/* I2C with hardware support*/
#define CONFIG_SYS_I2C_SPEED		500000	/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define PHYS_FLASH_1		0xBC000000 /* Flash Bank #1 */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_BANK_SWITCH
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
#define CONFIG_SYS_FLASH_SIZE		64		/* flash size in MB */
#define CONFIG_SYS_FLASH_CACHE_BASE	0xA2000000

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/* The following #defines are needed to get flash environment right */
#define	CONFIG_SYS_MONITOR_BASE	TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_INIT_SP_OFFSET	0x800000
#define CONFIG_SYS_PAGED_FLASH_PAGESIZE 0x00400000

#define CONFIG_8BIT_ROM

/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_PAGED_FLASH_END	1

/* Address and size of Primary Environment Sector	*/
#define CONFIG_ENV_ADDR		0xBC0C0000
#define CONFIG_ENV_SIZE		0x2000	/* Size of the Environment		*/
#define CONFIG_ENV_OFFSET		0	/* starting right at the beginning	*/
#define CONFIG_ENV_SECT_SIZE	0x20000 /* Size of the Environment Sector	*/

#define CONFIG_EPI3_LOCATION    0xBC0E0000
#define CONFIG_EPI3_SIZE        0x20000

#define CONFIG_UBOOT_SIZE 	0xC0000
#define CONFIG_UBOOT_FLASH_BASE 0xBC000000
#define CONFIG_UBOOT_ROM_BASE   0x83000000 /* Not actually the ROM base on this product. See bootmenu code */

#define CONFIG_NVS_LOCATION	0xBC800000
#define CONFIG_NVS_SIZE		0x80000
#define CONFIG_DIAG_NVS_BYTE_OFFSET	1

#define CONFIG_NR_DRAM_BANKS	1

#define CONFIG_JFFS2_PART_OFFSET 0x00100000
#define CONFIG_JFFS2_PART_SIZE   (atl_get_jffs2_part_size())
#define DIAG_USER_FLASH_OFFSET		CONFIG_JFFS2_PART_OFFSET
#define DIAG_USER_FLASH_SIZE		CONFIG_JFFS2_PART_SIZE

/* Place to store a copy of the ROM image before the
 * user removed the access jumper (8MB boundry)
 */
#define CONFIG_ROMIMAGE_BASE    CONFIG_UBOOT_ROM_BASE
#define CONFIG_DIAGMEM_BASE     0x81000000

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_DCACHE_SIZE		32768
#define CONFIG_SYS_ICACHE_SIZE		32768
#define CONFIG_SYS_CACHELINE_SIZE	16

/*
 *  memory configuration
 */

#define CONFIG_MEMDDR
#define CONFIG_DDRM64X16X1
//#define CONFIG_DDRM32X16X2
#define CONFIG_SDRM64X16X1

/*
 * PLD register address
 */
#define CONFIG_SYS_PLD_BASE		0xBCC00000
#define CONFIG_SYS_PLD_FLASH_CTL_REG	(CONFIG_SYS_PLD_BASE + (0x02 << 1))
#define CONFIG_SYS_PLD_RESET_CTL_REG	(CONFIG_SYS_PLD_BASE + (0x0D << 1))
#define CONFIG_SYS_PLD_FLASH_CTL_REG_WP	0x80

#define GPIO_SYSTEM_LED	0x00000001;
#define CONFIG_LED_FF	1

#endif	/* __CONFIG_H */
