/*
 * Allied Telesis AR660S board configuration file
 *
 * Based on P1_P2_RDB.h (2009.11) - please refer to it for more info
 *
 *
 * Copyright 2009 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_AR660
#ifdef CONFIG_MK_HYDROGEN0
#define CONFIG_P2020
#else
#define CONFIG_P1012
#endif

#define CONFIG_DIAGNOSTICS
#define CONFIG_DIAG_NOR_FLASH
#define CONFIG_DIAG_EPI3
#define CONFIG_DIAG_EPI3_PSU
#define CONFIG_MAX_PSU 1
#define CONFIG_BOOTMENU
#define CONFIG_FIT

#ifdef CONFIG_MK_HYDROGEN0
#define CONFIG_COMPATIBLE_DEVICES       \
{                                       \
	{ 354, "Hydrogen-0" },		\
	{ 0, NULL }			\
}
#else
#define CONFIG_COMPATIBLE_DEVICES       \
{                                       \
	{ 354, "AT-AR660S" },		\
	{ 0, NULL }			\
}
#endif
#define CONFIG_THIS_DEVICE	5

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48/P1020/P2020,etc*/
#define CONFIG_FSL_ELBC		1	/* Enable eLBC Support */
#define CONFIG_PCI		1	/* Enable PCI/PCIE */
#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_SYS_CLK_FREQ	66666000 /* DDRCLK on AR660 */
#define CONFIG_DDR_CLK_FREQ	CONFIG_SYS_CLK_FREQ /* SYS_CLK and DDR_CLK use the same source */

#if defined(CONFIG_P2020) || defined(CONFIG_P1020)
#define CONFIG_MP
#endif

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */

#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */

#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
#define CONFIG_MISC_INIT_R		1	/* Call misc_init_f */

#define CONFIG_ENABLE_36BIT_PHYS	1

#define CONFIG_SYS_MEMTEST_START	0x00010000	/* skip exception vectors */
#define CONFIG_SYS_MEMTEST_END		0x0fffffff
#define CONFIG_PANIC_HANG	/* do not reset board on panic */

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_CCSRBAR_PHYS		0xfffe00000ull /* physical addr of CCSRBAR */
#else
#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR
#endif
#define CONFIG_SYS_IMMR	CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */

#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */

#define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR+0xa000)

/* DDR Setup */
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_DLL

#define CONFIG_MEM_INIT_VALUE	0xdeadbeef

#define CONFIG_SYS_SDRAM_SIZE		256 	/* DDR size on AR660 */
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	1

#define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
#define CONFIG_SYS_DDR_SBE		0x00FF0000

/* These are used when DDR doesn't use SPD. */
#define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
#define CONFIG_SYS_DDR_CS0_CONFIG       0x80014102
#define CONFIG_SYS_DDR_TIMING_3         0x00020000
#define CONFIG_SYS_DDR_TIMING_0         0x00320202
#define CONFIG_SYS_DDR_TIMING_1         0x5e593543
//#define CONFIG_SYS_DDR_TIMING_2         0x42a06cd1
#define CONFIG_SYS_DDR_TIMING_2         0x4fa06cd1
#define CONFIG_SYS_DDR_SDRAM_CFG	0x43080000
#define CONFIG_SYS_DDR_SDRAM_CFG_2	0x04401010
#define CONFIG_SYS_DDR_SDRAM_MODE	0x00200952
#define CONFIG_SYS_DDR_SDRAM_MODE_2	0x00000000
#define CONFIG_SYS_DDR_SDRAM_INTERVAL	0x09c44e20
#define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x02800000
#define CONFIG_SYS_DDR_TIMING_4         0x00000000   /* for DDR3 memory */
#define CONFIG_SYS_DDR_TIMING_5         0x00000000   /* for DDR3 memory */
#define CONFIG_SYS_DDR_ZQ_CNTL		0x00000000   /* for DDR3 memory */
#define CONFIG_SYS_DDR_WRLVL_CNTL	0x00000000   /* for DDR3 memory */
#define CONFIG_SYS_DDR_CDR_1		0x00000000
#define CONFIG_SYS_DDR_CDR_2		0x00000000
#define CONFIG_SYS_DDR_OCD_CTRL		0x00000000
#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
//#define CONFIG_SYS_DDR_CONTROL		0xC3080000	/* Type = DDR2 */
//#define CONFIG_SYS_DDR_CONTROL2		0x04401010

/*
 * Physical Memory Map
 *
 * 0x0000_0000	0x1fff_ffff	DDR			512M cacheable
 * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
 * 0xec00_0000	0xefff_ffff	FLASH			64M non-cacheable
 * 0xf700_0000	0xf700_0fff	CPLD			4K non-cacheable
 * 0xf710_0000	0xf717_ffff	NVS/BBSRAM		512K cacheable
 * 0xf720_0000	0xf723_ffff	PIC0			256K non-cacheable
 * 0xf730_0000	0xf733_ffff	PIC1			256K non-cacheable
 * 0xf7c0_0000	0xf7c3_ffff	PCI IO range		256K non-cacheable
 * 0xf7d0_0000	0xf7d0_3fff	L1 for stack		16K cacheable
 * 0xffc0_0000	0xffff_ffff	FLASH (AS=1)		4M non-cacheable
 * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
 * 0xffff_f000	0xffff_ffff	Reset Page      	4K non-cacheable

 */

/*
 * Local Bus Definitions
 */
#define CONFIG_SYS_FLASH_BASE		0xec000000	/* start of FLASH 64M */
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
#define CONFIG_FLASH_SIZE		0x02000000 /* Our chips represent themselves as 1x64MB */

#define CONFIG_SYS_CPLD_BASE		0xf7000000
#define CONFIG_SYS_CPLD_BASE_PHYS	CONFIG_SYS_CPLD_BASE

#define CONFIG_NVS_LOCATION		0xf7100000
#define CONFIG_NVS_LOCATION_PHYS	CONFIG_NVS_LOCATION
#define CONFIG_NVS_SIZE			0x80000

#ifndef CONFIG_MK_HYDROGEN0
#define CONFIG_SYS_PIC0_BASE		0xf7200000
#define CONFIG_SYS_PIC0_BASE_PHYS	CONFIG_SYS_PIC0_BASE
#define CONFIG_SYS_PIC1_BASE		0xf7300000
#define CONFIG_SYS_PIC1_BASE_PHYS	CONFIG_SYS_PIC1_BASE
#endif

#define CONFIG_JFFS2_PART_OFFSET 0x0
#define CONFIG_JFFS2_PART_SIZE atl_get_jffs2_part_size()
#define DIAG_USER_FLASH_OFFSET		CONFIG_JFFS2_PART_OFFSET
#define DIAG_USER_FLASH_SIZE		CONFIG_JFFS2_PART_SIZE

#define CONFIG_FLASH_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
					BR_PS_16 | BR_V)
#define CONFIG_FLASH_OR_PRELIM		(OR_AM_64MB \
					| OR_GPCM_BCTLD \
					| OR_GPCM_CSNT \
					| OR_GPCM_SCY_10)

#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM	/* NOR Options */

#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE

#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
#define CONFIG_UBOOT_FLASH_BASE 	TEXT_BASE
#define CONFIG_UBOOT_SIZE 		0x80000
#define CONFIG_UBOOT_ROM_BASE 		0xfff80000
#define CONFIG_SYS_STDALONE_APP_SIZE	0x40000

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7

#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
#define CONFIG_HWCONFIG



/* other OR/BR settings */
/* NVS config */
#define CONFIG_NVS_BR_PRELIM	(CONFIG_NVS_LOCATION_PHYS \
				| BR_PS_8	/* Port Size = 8 bit */ \
				| BR_V)			/* valid */

#define CONFIG_NVS_OR_PRELIM	(OR_AM_512KB		/* length 512K */ \
				| OR_GPCM_BCTLD \
				| OR_GPCM_CSNT \
				| OR_GPCM_SCY_6)

#define CONFIG_SYS_BR1_PRELIM  CONFIG_NVS_BR_PRELIM  /* NVS Base Address */
#define CONFIG_SYS_OR1_PRELIM  CONFIG_NVS_OR_PRELIM  /* NVS Options */

#define CONFIG_CPLD_BR_PRELIM	(CONFIG_SYS_CPLD_BASE \
				| BR_PS_8	/* Port Size = 8 bit */ \
				| BR_V)			/* valid */

#define CONFIG_CPLD_OR_PRELIM	(OR_AM_64KB \
				| OR_GPCM_BCTLD \
				| OR_GPCM_CSNT \
				| OR_GPCM_SCY_6)

#define CONFIG_SYS_BR2_PRELIM  CONFIG_CPLD_BR_PRELIM  /* CPLD Base Address */
#define CONFIG_SYS_OR2_PRELIM  CONFIG_CPLD_OR_PRELIM  /* CPLD Options */

#ifdef CONFIG_SYS_PIC0_BASE
#define CONFIG_PIC0_BR_PRELIM	(CONFIG_SYS_PIC0_BASE \
				| BR_PS_8	/* Port Size = 8 bit */ \
				| BR_V)			/* valid */

#define CONFIG_PIC0_OR_PRELIM	(OR_AM_64KB \
				| OR_GPCM_CSNT \
				| OR_GPCM_SCY_6)

#define CONFIG_SYS_BR3_PRELIM  CONFIG_PIC0_BR_PRELIM  /* PIC0 Base Address */
#define CONFIG_SYS_OR3_PRELIM  CONFIG_PIC0_OR_PRELIM  /* PIC0 Options */
#else
#define CONFIG_SYS_BR3_PRELIM 0
#define CONFIG_SYS_OR3_PRELIM 0
#endif

#ifdef CONFIG_SYS_PIC1_BASE
#define CONFIG_PIC1_BR_PRELIM	(CONFIG_SYS_PIC1_BASE \
				| BR_PS_8	/* Port Size = 8 bit */ \
				| BR_V)			/* valid */

#define CONFIG_PIC1_OR_PRELIM	(OR_AM_64KB \
				| OR_GPCM_CSNT \
				| OR_GPCM_SCY_6)

#define CONFIG_SYS_BR4_PRELIM  CONFIG_PIC1_BR_PRELIM  /* PIC1 Base Address */
#define CONFIG_SYS_OR4_PRELIM  CONFIG_PIC1_OR_PRELIM  /* PIC1 Options */
#else
#define CONFIG_SYS_BR4_PRELIM 0
#define CONFIG_SYS_OR4_PRELIM 0
#endif

#define CONFIG_SYS_BR5_PRELIM 0
#define CONFIG_SYS_OR5_PRELIM 0

#define CONFIG_SYS_BR6_PRELIM 0
#define CONFIG_SYS_OR6_PRELIM 0

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xf7d00000 	/* stack in RAM */
#define CONFIG_SYS_INIT_RAM_END		0x00004000	/* End of used area in RAM */

#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END \
						- CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/* Serial Port - controlled on board with jumper J8
 * open - index 2
 * shorted - index 1
 */
#define CONFIG_CONS_INDEX	1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef	CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif

/*
 * Pass open firmware flat tree
 */
#define CONFIG_OF_LIBFDT		1
#define CONFIG_OF_BOARD_SETUP		1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/* I2C */
#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
#define CONFIG_HARD_I2C		/* I2C with hardware support */
#undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
#define CONFIG_SYS_I2C_SPEED		80000	/* I2C speed and slave address*/
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_NOPROBES	{{0}}	/* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET		0x3000
#define CONFIG_SYS_I2C2_OFFSET		0x3100

#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR                0x68

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */

/* controller 1, Slot 1, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT	0xb0000000
#define CONFIG_SYS_PCIE1_MEM_BUS	0xb0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xb0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xf7c30000
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xf7c30000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */

#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP			/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#undef CONFIG_RTL8139

#ifdef CONFIG_RTL8139
/* This macro is used by RTL8139 but not defined in PPC architecture */
#define KSEG1ADDR(x)		(x)
#define _IO_BASE	0x00000000
#endif


#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_DOS_PARTITION

#endif	/* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI	1
#endif

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
//#define CONFIG_TSEC1	1
//#define CONFIG_TSEC1_NAME	"eTSEC1"
//#define CONFIG_TSEC2	1
//#define CONFIG_TSEC2_NAME	"eTSEC2"
#define CONFIG_TSEC3	1
#define CONFIG_TSEC3_NAME	"eTSEC3"

//#define TSEC1_PHY_ADDR		2
//#define TSEC2_PHY_ADDR		0
#define TSEC3_PHY_ADDR		0x10

#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)

//#define TSEC1_PHYIDX		0
//#define TSEC2_PHYIDX		0
#define TSEC3_PHYIDX		0

#define CONFIG_ETHPRIME		"eTSEC3"

#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
#endif	/* CONFIG_TSEC_ENET */

/* GPIO setup */
#define CONFIG_SYS_GPDIR_VAL	0x00000000
#define CONFIG_SYS_GPODR_VAL	0x00000000
#define CONFIG_SYS_GPIMR_VAL	0x00000000
#define CONFIG_SYS_GPICR_VAL	0x00000000

/* GPIO output pin initial states are
 * 1. Fault LED off (GPIO 10, 1=off)
 * 2. Both Master LEDs off (GPIOS 8 & 9, 1=off)
 * 3. POE held in reset (GPIO 12, 0=reset)
 * 4. EEPROM write protect on (GPIO 14, 1=protect)
 * 5. Stack module in reset (GPIO 15, 0=reset)
 */
#define CONFIG_SYS_GPDAT_INIT_VAL	0x00E20000


/*
 * Environment
 */

#if defined(CONFIG_SYS_RAMBOOT)
	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
	#define CONFIG_ENV_SIZE		0x2000
#else
	#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
	#define CONFIG_ENV_ADDR		0xfff80000
	#else
	#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - (CONFIG_ENV_SECT_SIZE + CONFIG_SYS_STDALONE_APP_SIZE))
	#endif
	#define CONFIG_ENV_SIZE		0x2000
	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

#define CONFIG_DIAGMEM_BASE  0x1000000
#define CONFIG_EPI3_LOCATION (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
#define CONFIG_EPI3_SIZE CONFIG_ENV_SECT_SIZE

#include <configs/atl-std-opts.h>

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>
// undefine some of the defaults we don't want
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_XIMG

#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR

#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#define CONFIG_CMD_NET
#endif

#define CONFIG_MMC     1
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#endif

#define CONFIG_USB_EHCI
#define CONFIG_EHCI_SMBUS_RESET 1

#ifdef CONFIG_USB_EHCI
#define CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#define CONFIG_USB_STORAGE
#endif

#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION

//#define CONFIG_MMC_SPI
//#define CONFIG_ESPI
//#define CONFIG_ESPI_CS		0
//#define CONFIG_CMD_FAT
//#define CONFIG_DOS_PARTITION
//#define CONFIG_MMC_MAX_FREQ	20000000

/* Support lzma decompression */
#define CONFIG_LZMA

/* support the setup of the HUB */
#define IIC1_USB2512_ADDR	0x2c

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#ifdef CONFIG_MK_HYDROGEN0
#define CONFIG_SYS_PROMPT	"Hydrogen-0> "	/* Monitor Command Prompt */
#else
#define CONFIG_SYS_PROMPT	"AR660S> "		/* Monitor Command Prompt */
#endif
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#endif

#define CONFIG_HOSTNAME		unknown
#define CONFIG_ROOTPATH		/opt/nfsroot
#define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */

#endif	/* __CONFIG_H */
