/*
 * Copyright 2010 Allied Telesis.
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <X.Xiao@motorola.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * Allied Telesis x900 board configuration file
 *
 * Based on MPC8540ADS.h (2009.11) - please refer to it for more info
 *
 */

#ifndef __CONFIG_H
#define __CONFIG_H

//#define DEBUG

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_MPC85xx		1	/* MPC854x/MPC856x */
#define CONFIG_MPC8541		1	/* MPC8541 specific */
#define CONFIG_MPC8540ADS	1	/* MPC8540ADS board specific */
#define CONFIG_CPM2		1	/* Has CPM2 */
#define CONFIG_x900             1	/* x900 board specific */

#define CONFIG_ATLAT9924TS
#define CONFIG_NUM_XEMS         2
#define CONFIG_THIS_DEVICE	1	/* x900-X */
#define CONFIG_RELEASE_SPECIAL	1
#define CONFIG_COMPATIBLE_DEVICES	\
{					\
	{ 255,  "AT-9924Ts" },		\
	{ 256,  "AT-9924SPs" },		\
	{ 270,  "x900-24XT" },		\
	{ 271,  "x900-24XS" },		\
	{ 280,  "x900-24XT-N" },	\
	{ 287,  "x900-12XT/S" },	\
	{ 0, NULL }			\
}

#define CONFIG_DIAGNOSTICS
#define CONFIG_DIAG_NOR_FLASH
#define CONFIG_DIAG_EPI3
#define CONFIG_DIAGNOSTICS_SPLASH_RAPTOR
#define CONFIG_BOOTMENU

#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f */
#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r	*/

#define CONFIG_PCI
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW		1	/* Use common FSL init code */

/*
 * sysclk for MPC85xx
 *
 * Two valid values are:
 *    33000000
 *    66000000
 *
 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 * is likely the desired value here, so that is now the default.
 * The board, however, can run at 66MHz.  In any event, this value
 * must match the settings of some switches.  Details can be found
 * in the README.mpc85xxads.
 *
 * XXX -- Can't we run at 66 MHz, anyway?  PCI should drop to
 * 33MHz to accommodate, based on a PCI pin.
 * Note that PCI-X won't work at 33MHz.
 */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	33333000 /* ATL_CHANGE Use 33.333Mhz */
#endif


/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00400000


/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR		0xff700000	/* relocated CCSRBAR - ATL_CHANGE */
#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */

/* DDR Setup */
#define CONFIG_FSL_DDR1
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE

#define CONFIG_MEM_INIT_VALUE		0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS		0x55	/* CTLR 0 DIMM 0 */
#define SPD_EEPROM_ADDRESS_SECONDARY	0x51	/* For old base boards */

/* These are used when DDR doesn't use SPD. */
#define CONFIG_SYS_SDRAM_SIZE	128		/* DDR is 128MB */
#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
#define CONFIG_SYS_DDR_CS0_CONFIG	0x80000002
#define CONFIG_SYS_DDR_TIMING_1	0x37344321
#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
#define CONFIG_SYS_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
#define CONFIG_SYS_DDR_INTERVAL	0x05200100	/* autocharge,no open page */

/*
 * SDRAM on the Local Bus
 */
#define CONFIG_SYS_LBC_SDRAM_BASE	not used	/* Localbus SDRAM - ATL_CHANGE */
#define CONFIG_SYS_LBC_SDRAM_SIZE	0		/* LBC SDRAM is 0MB - ATL_CHANGE */

#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE	/* start of monitor */

#undef CONFIG_CLOCKS_IN_MHZ

#define CONFIG_CPLD_VERSION		0xff000010

#define CONFIG_DIAGMEM_BASE		0x01000000	/* Location in memory for use by diagnostics */

#define CONFIG_EPI3_SIZE		0x00020000
#define CONFIG_EPI3_LOCATION		atl_get_epi3_location()
#define CONFIG_EPI3_LOCATION_BASE	0xf9f00000

#define CONFIG_JFFS2_PART_OFFSET	0x00000000	/* Used by JFFS2 */
#define CONFIG_JFFS2_PART_SIZE		atl_get_jffs2_part_size()
#define CONFIG_JFFS2_PART_SIZE_BASE	0x01f00000	/* Used by JFFS2 & the AW+ upgrader/installer */
#define DIAG_USER_FLASH_OFFSET		CONFIG_JFFS2_PART_OFFSET
#define DIAG_USER_FLASH_SIZE		CONFIG_JFFS2_PART_SIZE

#define CONFIG_UBOOT_ROM_BASE		0xfff40000	/* Used only by the AW+ upgrader/installer */
#define CONFIG_UBOOT_FLASH_BASE		atl_get_uboot_flash_base()
#define CONFIG_UBOOT_FLASH_BASE_BASE	0xf9f40000	/* Used only by the AW+ upgrader/installer */
#define CONFIG_UBOOT_SIZE		0x000c0000	/* Used only by the AW+ upgrader/installer & diagnostics */

/*
 * Local Bus Definitions
 */
#define CONFIG_SYS_BOOTROM_BASE		0xfff00000	/* start of FLASH Boot ROM 1M */
#define CONFIG_SYS_BR0_PRELIM		0xfff01001	/* port size 16bit - ATL_CHANGE */
#define CONFIG_SYS_OR0_PRELIM		0xfff00c80	/* 1MB FLASH ROM - ATL_CHANGE */

#define CONFIG_SYS_FLASH_BASE		0xf8000000	/* start of whole FLASH 32/64M */
#define CONFIG_SYS_BR1_PRELIM		0xf8001001
#define CONFIG_SYS_OR1_PRELIM		0xfc000c80	/* 64MB Flash at 0xf8000000 */

#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks - ATL_CHANGE */
#define CONFIG_SYS_FLASH_SIZE		64		/* 64MB Flash Max */
#define CONFIG_SYS_MAX_FLASH_SECT	260		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ { 0xf9f00000 + atl_get_offset_from_base(), 0x100000 } }

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO

#define CONFIG_NVS_LOCATION		0xfe000000
#define CONFIG_NVS_SIZE			0x00080000
#define CONFIG_SYS_SRAM_BASE		0xfe000000	/* start of NVS SRAM 512KB */
#define CONFIG_SYS_BR2_PRELIM		0xfe000801
#define CONFIG_SYS_OR2_PRELIM		0xfff80c34

#define CONFIG_SYS_EPLD_BASE		0xff000000	/* start of EPLD 64KB */
#define CONFIG_SYS_BR3_PRELIM		0xff000801
#define CONFIG_SYS_OR3_PRELIM		0xffff0844

#define CONFIG_SYS_LBC_LCRR		0x80000008    /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/

#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_BSMA1516	\
				| LSDMR_RFCR5		\
				| LSDMR_PRETOACT3	\
				| LSDMR_ACTTORW3	\
				| LSDMR_BL8		\
				| LSDMR_WRC2		\
				| LSDMR_CL3		\
				| LSDMR_RFEN		\
				)

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef  CONFIG_SYS_RAMBOOT
#endif

/*
 * SDRAM Controller configuration sequence.
 */
#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)


#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END		0x00004000	/* End of used area in RAM */

#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/* Serial Port */
#define CONFIG_CONS_INDEX     1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE    1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef  CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT		1
#define CONFIG_OF_BOARD_SETUP		1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

#define CONFIG_SYS_64BIT_VSPRINTF	1
#define CONFIG_SYS_64BIT_STRTOUL	1

/*
 * I2C
 */
#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
#define CONFIG_HARD_I2C		/* I2C with hardware support*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET		0x3000

/* RapidIO MMU */
#define CONFIG_SYS_RIO_MEM_VIRT	0xc0000000	/* base address */
#define CONFIG_SYS_RIO_MEM_BUS	0xc0000000	/* base address */
#define CONFIG_SYS_RIO_MEM_PHYS	0xc0000000
#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_SYS_PCI1_MEM_VIRT	0x40000000	/* ATL_CHANGE */
#define CONFIG_SYS_PCI1_MEM_BUS		0x40000000	/* ATL_CHANGE */
#define CONFIG_SYS_PCI1_MEM_PHYS	0x40000000	/* ATL_CHANGE */
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */

#define CONFIG_SYS_PCI2_MEM_VIRT	0x60000000	/* ATL_CHANGE */
#define CONFIG_SYS_PCI2_MEM_BUS		0x60000000	/* ATL_CHANGE */
#define CONFIG_SYS_PCI2_MEM_PHYS	0x60000000	/* ATL_CHANGE */
#define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */

#define CONFIG_SYS_PCI1_IO_VIRT		0xa2000000	/* ATL_CHANGE */
#define CONFIG_SYS_PCI1_IO_BUS		0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS		0xa2000000	/* ATL_CHANGE */
#define CONFIG_SYS_PCI1_IO_SIZE		0x01000000	/* 16M - ATL_CHANGE */

#define CONFIG_SYS_PCI2_IO_VIRT		0xa3000000	/* ATL_CHANGE */
#define CONFIG_SYS_PCI2_IO_BUS		0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS		0xa3000000	/* ATL_CHANGE */
#define CONFIG_SYS_PCI2_IO_SIZE		0x01000000	/* 16M - ATL_CHANGE */

#if defined(CONFIG_PCI)

#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP			/* do pci plug-and-play */
#define CONFIG_MPC85XX_PCI2

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
    #define PCI_ENET0_IOADDR	0xe0000000
    #define PCI_ENET0_MEMADDR	0xe0000000
    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
#endif

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */


#if defined(CONFIG_TSEC_ENET)

#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI	1
#endif

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define TSEC1_PHY_ADDR		1	/* ATL_CHANGE */
#define TSEC1_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define CONFIG_M88E1111_PHY	1	/* ATL_CHANGE */


#if CONFIG_HAS_FEC
#define CONFIG_MPC85XX_FEC	1
#define CONFIG_MPC85XX_FEC_NAME		"FEC"
#define FEC_PHY_ADDR		3
#define FEC_PHYIDX		0
#define FEC_FLAGS		0
#endif

/* Options are: TSEC[0-1], FEC */
#define CONFIG_ETHPRIME		"TSEC0"

#endif	/* CONFIG_TSEC_ENET */


/*
 * Environment
 */

/* env code is hacked for "moving" location.
 * env is located at the top of flash so if a device
 * has more flash installed, the env is in a different location.
 * this is pretty ugly but it's a bit too late to fix it both
 * from the hardware and software point of view.
 */
#define ATL_CONFIG_SYS_ENV_LOCATION_NOT_FIXED
#define CONFIG_ENV_ADDR_BASE	0xf9f20000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env - ATL_CHANGE */
#define CONFIG_ENV_SIZE		0x2000

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

#if defined(CONFIG_SYS_RAMBOOT)
    #undef CONFIG_CMD_SAVEENV
    #undef CONFIG_CMD_LOADS
#endif

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
#define CONFIG_SYS_PROMPT	"x900> "	/* Monitor Command Prompt - ATL_CHANGE */

#if defined(CONFIG_CMD_KGDB)
    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#endif

#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif


/*
 * Environment Configuration
 */

#define CONFIG_HOSTNAME		unknown
#define CONFIG_ROOTPATH		/nfsroot
#define CONFIG_BOOTFILE		your.uImage

#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */

#define CONFIG_NFSBOOTCOMMAND	                                        \
   "setenv bootargs root=/dev/nfs rw "                                  \
      "nfsroot=$serverip:$rootpath "                                    \
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $loadaddr $bootfile;"                                          \
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND \
   "setenv bootargs root=/dev/ram rw "                                  \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $ramdiskaddr $ramdiskfile;"                                    \
   "tftp $loadaddr $bootfile;"                                          \
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND

#define CONFIG_MMC_SPI
#define CONFIG_SPI
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#define CONFIG_MMC_MAX_FREQ	25000000

#include <configs/atl-std-opts.h>

//#undef CONFIG_SILENT_CONSOLE

#endif	/* __CONFIG_H */
