/*
 * Board config file for ATL AR570
 *
 * Allied Telesis Labs
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_THIS_DEVICE 	4
#define CONFIG_COMPATIBLE_DEVICES 	\
{ 					\
	{ 257, "AT-AR570S" },		\
	{ 277, "AT-AR770S" },		\
	{ 0, NULL }			\
}

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560 */
#define CONFIG_CPM2		1	/* has CPM2 */
#define CONFIG_MPC8555		1	/* MPC8555 specific */

//#define CONFIG_PCI
#define CONFIG_DX160_TSEC_ENET 		/* dx160 to tsec ethernet support */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_DDR_ECC			/* only for ECC DDR module */
#define CONFIG_MEM_INIT_VALUE		0xDeadBeef

#define CONFIG_DDR_DLL			/* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */

#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */

#define CONFIG_MISC_INIT_R		/* Need to do ATR RD1 specific init */

/*
 * sysclk for MPC85xx
 *
 * Two valid values are:
 *    33000000
 *    66000000
 *
 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 * is likely the desired value here, so that is now the default.
 * The board, however, can run at 66MHz.  In any event, this value
 * must match the settings of some switches.  Details can be found
 * in the README.mpc85xxads.
 */
#define CONFIG_SYS_CLK_FREQ	33333000


/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */
#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */

#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */

#undef	CFG_DRAM_TEST			/* memory test, takes time */
#define CFG_MEMTEST_START	0x00200000	/* memtest region */
#define CFG_MEMTEST_END		0x00400000


/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
#define CFG_CCSRBAR		0xff700000	/* relocated CCSRBAR */
#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */


/*
 * DDR Setup
 */
#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE

#if defined(CONFIG_SPD_EEPROM)
    /*
     * Determine DDR configuration from I2C interface.
     */
    #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */

#else
    /*
     * Manually set up DDR parameters
     */
    #define CFG_SDRAM_SIZE	128		/* DDR is 128MB */
    #define CFG_DDR_CS0_BNDS	0x00000007	/* 0-256MB */
    #define CFG_DDR_CS0_CONFIG	0x80000101
    #define CFG_DDR_CS1_BNDS	0x00000000	/* 0-512MB */
    #define CFG_DDR_CS1_CONFIG	0x00000000
    #define CFG_DDR_TIMING_1	0x36332221
    #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
    #define CFG_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
    #define CFG_DDR_MODE	0x00020062	/* DLL,normal,seq,4/2.5 */
    #define CFG_DDR_INTERVAL	0x04120100	/* autocharge,no open page */
#endif

/*
 * SDRAM on the Local Bus
 */
#define CFG_LBC_SDRAM_BASE	0xf8000000	/* Localbus SDRAM */
#define CFG_LBC_SDRAM_SIZE	0		/* LBC SDRAM is 0MB */

/* Setup the 32 MB of FLASH */
#define CFG_FLASH_BASE		0xf8000000	/* start of FLASH 8M */

/* Setup the initial CS0 to map 1MB of FLASH at 0xfff00000 */
#define CFG_BR0_PRELIM		0xfff01101	/* port size 16bit */
#define CFG_OR0_PRELIM		0xfff00c70	/* 1MB Flash */

#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
#undef	CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */

#define CFG_FLASH_CFI                         /* The flash is CFI compatible  */
//#define CFG_FLASH_CFI_DRIVER                  /* Use common CFI driver        */


#undef CONFIG_CLOCKS_IN_MHZ

#define CONFIG_DIAGMEM_BASE 	0x01000000
#define CONFIG_UBOOT_SIZE 	0x00040000
#define CONFIG_UBOOT_FLASH_BASE 0xF9FC0000


#define CONFIG_EPI3_SIZE        0x00020000
#define CONFIG_EPI3_LOCATION    0xf9fa0000


#define CONFIG_JFFS2_PART_OFFSET 0x0
#define CONFIG_JFFS2_PART_SIZE  0x01f80000
                        
/*
 * Local Bus Definitions
 */
#define CFG_BR1_PRELIM		0xf8001001
#define CFG_OR1_PRELIM		0xfe000c70	/* 32MB Flash at 0xf8000000 */

#define CFG_BR2_PRELIM		0xfe000801
#define CFG_OR2_PRELIM		0xfff80886	/* PIC0 at 0xfe000000 8bit*/

#define CFG_BR3_PRELIM		0xfe080801
#define CFG_OR3_PRELIM		0xfff80886	/* PIC1 at 0xfe080000 8bit*/

#define CFG_BR4_PRELIM		0xff000801
#define CFG_OR4_PRELIM		0xffff0844	/* CPLD at 0xff000000 8bit*/
#define CFG_CPLD_BASE           0xff000000

#define CFG_BR5_PRELIM		0xff100801
#define CFG_OR5_PRELIM		0xfff80c34	/* NVS at 0xff100000 8bit*/
#define CFG_SRAM_BASE           0xff100000
 
#define CFG_LBC_LCRR		0x80000008    /* LB clock ratio reg */
#define CFG_LBC_LBCR		0x00000000    /* LB config reg */

#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 	1
#define CFG_INIT_RAM_ADDR	0xa0000000	/* Initial RAM address */
#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */

#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET


/* Serial Port */
#define CONFIG_CONS_INDEX     1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE    1
#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)


/* I2C */
// #define  CONFIG_HARD_I2C		/* I2C with hardware support*/
// #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
// #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
// #define CFG_I2C_SLAVE		0x7F
// #define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */

/* RapidIO MMU */
#define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CFG_PCI1_MEM_BASE	0x80000000
#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CFG_PCI1_IO_BASE	0xe2000000
#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE	0x0		/* 06M */

#define CFG_PCI2_MEM_BASE	0xa0000000
#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
#define CFG_PCI2_IO_BASE	0xe3000000
#define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */


#if defined(CONFIG_DX160_TSEC_ENET)

#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 	1
#endif

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_RGMII		1	/* Reduced-GMII PHY interface */
#define CONFIG_DX160_MPC85XX_TSEC1	1
#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
#define TSEC1_PHY_ADDR		16
#define TSEC1_PHYIDX		0

#define CONFIG_ETHPRIME		"MOTO ENET0"

#endif	/* CONFIG_TSEC_ENET */


#define CFG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
  
#define CFG_ENV_ADDR	  0xf9f80000 /* the env block is two sectors before the u-boot image in flash */
#define CFG_ENV_SIZE		0x2000

#include <configs/atl-std-opts.h>

#define CONFIG_COMMANDS         ( CONFIG_GENERIC_COMMANDS )

#include <cmd_confdefs.h>

#define CFG_PROMPT	"AR570> "		/* Monitor Command Prompt */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/

/* Cache Configuration */
#define CFG_DCACHE_SIZE		32768
#define CFG_CACHELINE_SIZE	32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot */

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif


#endif	/* __CONFIG_H */
