/*
 * atlat9924T.h
 * Matthew Millman
 */

/*
 * Configuration settings for the at9924t board.
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_THIS_DEVICE 	2 	/* x900 */
#define CONFIG_COMPATIBLE_DEVICES 		\
{ 						\
	{ 201, "AT-8948" },			\
	{ 202, "AT-8948i    x900-48FE" },	\
	{ 278, "AT-8948i-N  x900-48FE-N" },	\
	{ 0, NULL }				\
}

#define CONFIG_DIAGNOSTICS
#define CONFIG_DIAG_EPI3
//#define CONFIG_DIAGNOSTICS_SPLASH_RAPTOR
#define CONFIG_BOOTMENU

/*
 * High Level Configuration Options
 * (easy to change)
 */

//#define CONFIG_COMPACTFLASH_PORTX

#define CONFIG_UBOOT_SIZE_VARIES

#define CFG_IDE_MAXBUS          1       
#define CFG_IDE_MAXDEVICE       1
#define CFG_IDE_8BIT

#ifdef CONFIG_COMPACTFLASH_PORTX
#define CFG_ATA_BASE_ADDR       0x70030000
#else
#define CFG_ATA_BASE_ADDR       0xFFE30000
#endif

#define CFG_ATA_IDE0_OFFSET     0x01F0
#define CFG_ATA_DATA_OFFSET     0x0000
#define CFG_ATA_REG_OFFSET      0x0000

#define CONFIG_DOS_PARTITION
#define CONFIG_IDE_LED
#define CONFIG_EXT_IDE_LED
#define CONFIG_COMPACTFLASH /* Only used by our bootmenu */
#define CONFIG_IDE_PREINIT

#define CONFIG_PCI

#define CONFIG_HARD_I2C
#define CFG_I2C_SPEED 		0
#define CFG_I2C_SLAVE 		0
#define SPD_EEPROM_ADDRESS 	0x51
#define CONFIG_SPD_EEPROM

/* *CAUTION* *CAUTION* */
#define _IO_BASE 0xFE000000
/* This define is a hack!
 * It's here to avoid hacking up the PCNet32 driver
 * to allow for the fact that the PCI view of the IO
 * window differs to the CPU view.
 *
 * It will probably break anything else that tries to use
 * inb() outb() inw() outw() inl() outl() in memory mapped space
 */

//#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCNET
#define CONFIG_PCNET_79C973
 
#define CONFIG_MPC824X		1
#define CONFIG_MPC8245		1

#define CONFIG_CONS_INDEX	1

#define CONFIG_ENV_OVERWRITE

/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
 */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"AT8948> "		/* Monitor Command Prompt	*/
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/

#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#endif

#define CONFIG_HW_WATCHDOG
#define CFG_WATCHDOG_FREQ       (CFG_HZ / 10)
#define CONFIG_MISC_INIT_R

/* Print Buffer Size
 */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE	    0x00000000

#define CFG_EUMB_ADDR       0x80100000

#define CFG_MONITOR_BASE    TEXT_BASE

#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/

#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
#undef CFG_RAMBOOT
#else
#define CFG_RAMBOOT
#endif

#define CONFIG_EPI3_LOCATION    0x040E0000
#define CONFIG_EPI3_SIZE        0x20000


#define CFG_GBL_DATA_SIZE    128

#define CFG_INIT_RAM_ADDR     0x08000000 /* 256MB marker */


#define CFG_INIT_RAM_END      0x1000
#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)

/*
 * NS16550 Configuration
 */
#define CFG_NS16550
#define CFG_NS16550_SERIAL

#define CFG_NS16550_REG_SIZE	1

#define CFG_NS16550_CLK		3686400

#define CFG_NS16550_COM1        0xFFE20040	

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * For the detail description refer to the MPC8240 user's manual.
 */

#define CONFIG_SYS_CLK_FREQ  33000000
#define CFG_HZ		     1000
#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3


/* Memory bank settings.
 * Only bits 20-29 are actually used from these vales to set the
 * start/end addresses. The upper two bits will always be 0, and the lower
 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 * address. Refer to the MPC8240 book.
 */

#define CFG_BANK0_START	    0x00000000
#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
#define CFG_BANK0_ENABLE    1
#define CFG_BANK1_START	    0x3ff00000
#define CFG_BANK1_END	    0x3fffffff
#define CFG_BANK1_ENABLE    0
#define CFG_BANK2_START	    0x3ff00000
#define CFG_BANK2_END	    0x3fffffff
#define CFG_BANK2_ENABLE    0
#define CFG_BANK3_START	    0x3ff00000
#define CFG_BANK3_END	    0x3fffffff
#define CFG_BANK3_ENABLE    0
#define CFG_BANK4_START	    0x3ff00000
#define CFG_BANK4_END	    0x3fffffff
#define CFG_BANK4_ENABLE    0
#define CFG_BANK5_START	    0x3ff00000
#define CFG_BANK5_END	    0x3fffffff
#define CFG_BANK5_ENABLE    0
#define CFG_BANK6_START	    0x3ff00000
#define CFG_BANK6_END	    0x3fffffff
#define CFG_BANK6_ENABLE    0
#define CFG_BANK7_START	    0x3ff00000
#define CFG_BANK7_END	    0x3fffffff
#define CFG_BANK7_ENABLE    0

#define CFG_ODCR	    0xff

/* RAM */

#define CFG_IBAT0U	(0x00000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT0L 	(0x00000000 | BATL_MEMCOHERENCE | BATL_PP_10)

//.equ RAMIBATU , SYSTEM_MEMORY_VIRTUAL_BASE+BLOCK_256M+VALID_BOTH
//.equ RAMIBATL , SYSTEM_MEMORY_PHYSICAL_BASE+MEMCOHERENCE+MEMPROTECT_RW

/* ROM */

#define CFG_IBAT1U	(0xFFF00000 | BATU_BL_1M | BATU_VS | BATU_VP)
#define CFG_IBAT1L	(0xFFF00000 | BATL_MEMCOHERENCE | BATL_PP_10)

//.equ EPROMIBATU , SYSTEM_EPROM_VIRTUAL_BASE+BLOCK_1M+VALID_BOTH
//.equ EPROMIBATL , SYSTEM_EPROM_PHYSICAL_BASE+MEMCOHERENCE+MEMPROTECT_RW

/* Unused */

/* Actually this is used, for init ram */

//#define CFG_IBAT2U 	0x40000000 | BATU_BL_128K | BATU_VS | BATU_VP
//#define CFG_IBAT2L	0x40000000 | BATL_MEMCOHERENCE | BATL_PP_00

#define CFG_IBAT2L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT2U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)

//.equ UNUSED1IBATU , 0x40000000+BLOCK_128K+VALID_BOTH
//.equ UNUSED1IBATL , 0x40000000+MEMCOHERENCE+MEMPROTECT_RONLY

/* I-Bat for RAM (256-512M) */

#define CFG_IBAT3U	(0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT3L	(0x10000000 | BATL_MEMCOHERENCE | BATL_PP_10)

//.equ UNUSED2IBATU , 0x41000000+BLOCK_128K+VALID_BOTH
//.equ UNUSED2IBATL , 0x41000000+MEMCOHERENCE+MEMPROTECT_RONLY

/* RAM (0-255M) */

#define CFG_DBAT0U	(0x00000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT0L	(0x00000000 | BATL_MEMCOHERENCE | BATL_PP_10)

//.equ RAMDBATU	, SYSTEM_MEMORY_VIRTUAL_BASE+BLOCK_256M+VALID_BOTH
//.equ RAMDBATL , SYSTEM_MEMORY_PHYSICAL_BASE+MEMCOHERENCE+GUARDED+MEMPROTECT_RW

/* RAM (256-512M) */

#ifdef CONFIG_COMPACTFLASH_PORTX

#define CFG_DBAT1U	(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT1L	(0x70000000 | BATL_WRITETHROUGH | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE | BATL_GUARDEDSTORAGE | BATL_PP_10)

#else

#define CFG_DBAT1U	(0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT1L	(0x10000000 | BATL_MEMCOHERENCE | BATL_PP_10)

#endif

//#define CFG_DBAT1U      (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
//#define CFG_DBAT1L      (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)

//.equ RAMD1BATU , SYSTEM_MEMORY_VIRTUAL_BASE1+BLOCK_256M+VALID_BOTH
//.equ RAMD1BATL , SYSTEM_MEMORY_PHYSICAL_BASE1+MEMCOHERENCE+GUARDED+MEMPROTECT_RW

/* PCI */

#define CFG_DBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT2L	(0x80000000 | BATL_WRITETHROUGH | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE | BATL_GUARDEDSTORAGE | BATL_PP_10)

//.equ PCIMEMDBATU , PCI_MEMORY_VIRTUAL_BASE+BLOCK_256M+VALID_BOTH
//.equ PCIMEMDBATL , PCI_MEMORY_PHYSICAL_BASE+WRITETHRU+CACHE_INHIBIT+GUARDED+MEMCOHERENCE+MEMPROTECT_RW

/* IO */

#define CFG_DBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT3L	(0xF0000000 | BATL_WRITETHROUGH | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE | BATL_GUARDEDSTORAGE | BATL_PP_10)

//.equ IODBATU , IO_VIRTUAL_BASE+BLOCK_256M+VALID_BOTH
//.equ IODBATL , IO_PHYSICAL_BASE+WRITETHRU+CACHE_INHIBIT+MEMCOHERENCE+GUARDED+MEMPROTECT_RW

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */

#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	2	/* Max number of flash banks		*/
#define CFG_MAX_FLASH_SECT	128	/* Max number of sectors in one bank	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_REAL_BASE	0xFFE00000
#define CFG_FLASH_BASE		0x04000000
#define CFG_FLASH_PAGESELECT	0xFFE20000
//#define CFG_FLASH_PROTECTION

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM      CFG_FLASH_BASE  /* FLASH bank #0        */
#define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */

	/* Warining: environment is not EMBEDDED in the U-Boot code.
	 * It's stored in flash separately.
	 */

#define CFG_FLASH_CFI


#define CFG_PAGED_FLASH_END 0x05FFFFFF

#define CFG_ENV_EARLY_PAGE	0x6
#define ATL_CFG_ENV_EARLY_ADDR	0xFFFC0000
#define CFG_ENV_ADDR		0x040C0000
#define CFG_ENV_SIZE		0x2000	/* Size of the Environment		*/
#define CFG_ENV_OFFSET		0	/* starting right at the beginning	*/
#define CFG_ENV_SECT_SIZE	0x20000 /* Size of the Environment Sector	*/


#define CONFIG_8BIT_ROM /* Used by bootmenu */

#define CFG_FLASH_INCREMENT 1
#define CFG_FLASH_USE_BUFFER_WRITE
#define CFG_FLASH_PROTECTION

#define CONFIG_UBOOT_SIZE 0xC0000
#define CONFIG_UBOOT_FLASH_BASE 0x04000000
#define CONFIG_UBOOT_ROM_BASE 0xFFF00000

#define CONFIG_NVS_LOCATION 	0xFFE80000
#define CONFIG_NVS_SIZE		0x80000

#define CONFIG_JFFS2_PART_OFFSET 0x100000
#define CONFIG_JFFS2_PART_SIZE  0x1E00000

#define CONFIG_DIAGMEM_BASE     0x1000000

#include <configs/atl-std-opts.h>

				  
#define CONFIG_COMMANDS         ( CONFIG_GENERIC_COMMANDS | \
				  CFG_CMD_I2C | \
				  CFG_CMD_IDE | \
				  CFG_CMD_SDRAM )

#include <cmd_confdefs.h>
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_PCI			/* include pci support			*/
//#define CONFIG_PCI_PNP                  /* we need Plug 'n Play */
#define CONFIG_NET_MULTI		/* Multi ethernet cards support */
#define CFG_RX_ETH_BUFFER	8       /* use 8 rx buffer on eepro100  */
#endif /* __CONFIG_H */
