/*
 * (C) Copyright 2009, 2010
 * Allied Telesis <www.alliedtelesis.com>
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301 USA
 */

/* based on include/asm/arch-kirkwood/cpu.h */

#ifndef _DISCOCPU_H
#define _DISCOCPU_H

#include <asm/system.h>

#ifndef __ASSEMBLY__

#define DISCOCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
			| (attr << 8) | (disco_winctrl_calcsize(size) << 16))

#define DISCOGBE_PORT_SERIAL_CONTROL1_REG(_x)	\
		((_x ? DISCO_EGIGA0_BASE : DISCO_EGIGA1_BASE) + 0x44c)

#define DISCO_REG_DEVVEN_ID		(DISCO_REG_PCIE0_BASE + 0x0000)
#define DISCO_REG_CLASSREV_ID		(DISCO_REG_PCIE0_BASE + 0x0008)
#define DISCO_REG_SYSRST_CNT		(DISCO_MPP_BASE + 0x50)
#define SYSRST_CNT_1SEC_VAL		(25*1000000)
#define DISCO_REG_MPP_OUT_DRV_REG	(DISCO_MPP_BASE + 0xE0)

enum memory_bank {
	BANK0,
	BANK1,
	BANK2,
	BANK3
};

enum discocpu_winen {
	DISCOCPU_WIN_DISABLE,
	DISCOCPU_WIN_ENABLE
};

enum discocpu_target {
	DISCOCPU_TARGET_MEMORY = 0x1,
	DISCOCPU_TARGET_PCIE0 = 0x4,
	DISCOCPU_TARGET_PCIE1 = 0x8,
	DISCOCPU_TARGET_SASRAM = 0x9
};

enum discocpu_attrib {
	DISCOCPU_ATTR_DRAM_CS0 = 0x3e,
	DISCOCPU_ATTR_DRAM_CS1 = 0x3d,
	DISCOCPU_ATTR_DRAM_CS2 = 0x3b,
	DISCOCPU_ATTR_DRAM_CS3 = 0x37,
	DISCOCPU_ATTR_BOOTCS = 0x2f,
	DISCOCPU_ATTR_SPICS = 0x1f,
	
	DISCOCPU_ATTR_PCIE_LANE_0_IO = 0xe0,
	DISCOCPU_ATTR_PCIE_LANE_0_MEM = 0xe8,
	DISCOCPU_ATTR_PCIE_LANE_1_IO = 0xd0,
	DISCOCPU_ATTR_PCIE_LANE_1_MEM = 0xd8,
	DISCOCPU_ATTR_PCIE_LANE_2_IO = 0xb0,
	DISCOCPU_ATTR_PCIE_LANE_2_MEM = 0xb8,
	DISCOCPU_ATTR_PCIE_LANE_3_IO = 0x70,
	DISCOCPU_ATTR_PCIE_LANE_3_MEM = 0x78,

	DISCOCPU_ATTR_SASRAM_BYTE_SWAP = 0x00,
	DISCOCPU_ATTR_SASRAM_NO_SWAP = 0x01,
	DISCOCPU_ATTR_SASRAM_BYTE_WORD_SWAP = 0x02,
	DISCOCPU_ATTR_SASRAM_WORD_SWAP = 0x03

};

/*
 * Default Device Address MAP BAR values
 */
#define DISCO_DEFADR_PCI_MEM		0x90000000
#define DISCO_DEFADR_PCI_IO		0xC0000000
#define DISCO_DEFADR_PCI_IO_REMAP	0xC0000000
#define DISCO_DEFADR_SASRAM		0xC8010000
#define DISCO_DEFADR_NANDF		0xD8000000
#define DISCO_DEFADR_SPIF		0xE8000000
#define DISCO_DEFADR_BOOTROM		0xF8000000

/*
 * read feroceon/sheeva core extra feature register
 * using co-proc instruction
 */
static inline unsigned int readfr_extra_feature_reg(void)
{
	unsigned int val;
	asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
			(val)::"cc");
	return val;
}

/*
 * write feroceon/sheeva core extra feature register
 * using co-proc instruction
 */
static inline void writefr_extra_feature_reg(unsigned int val)
{
	asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
			(val):"cc");
	isb();
}

/*
 * MBus-L to Mbus Bridge Registers
 * Ref: Datasheet sec:A.2.1
 */
struct discowin_remap_registers {
	u32 ctrl;
	u32 base;
	u32 remap_lo;
	u32 remap_hi;
};

struct discowin_nonremap_registers {
	u32 ctrl;
	u32 base;
	u32 unused0;
	u32 unused1;
};

/*
 * CPU control and status Registers
 * Ref: Datasheet sec:A.3.2
 */
struct discocpu_registers {
	u32 config;	/*0x20100 */
	u32 ctrl_stat;	/*0x20104 */
	u32 rstoutn_mask; /* 0x20108 */
	u32 sys_soft_rst; /* 0x2010C */
	u32 ahb_mbus_cause_irq; /* 0x20110 */
	u32 ahb_mbus_mask_irq; /* 0x20114 */
	u32 pad1[2];
	u32 ftdll_config; /* 0x20120 */
	u32 pad2;
	u32 l2_cfg;	/* 0x20128 */
};

/*
 * Interrupt Controller Interface Registers
 * Ref: Datasheet sec:A.18
 */
struct discointr_registers {
	u32 iecr; /* 0x20200 */
	u32 icr_l; /* 0x20204 */
	u32 icr_h; /* 0x20208 */
	u32 imer; /* 0x2020c */
	u32 imr_l; /* 0x20210 */
	u32 imr_h; /* 0x20214 */
	u32 scr; /* 0x20218 */
	u32 fimer; /* 0x2021c */
	u32 fimr_l; /* 0x20220 */
	u32 fimr_h; /* 0x20224 */
	u32 fscr; /* 0x20228 */
	u32 eimer; /* 0x2022c */
	u32 eimr_l; /* 0x20230 */
	u32 eimr_h; /* 0x20234 */
	u32 escr; /* 0x20238 */
};

/*
 * GPIO Registers
 * Ref: Datasheet sec:A.19
 */
struct discogpio_registers {
	u32 dout;
	u32 oe;
	u32 blink_en;
	u32 din_pol;
	u32 din;
	u32 irq_cause;
	u32 irq_mask;
	u32 irq_level;
	u32 dout_set;
	u32 dout_clear;
	u32 oe_set;
	u32 oe_clear;
};

/*
 * functions
 */
void reset_cpu(unsigned long ignored);
unsigned char get_random_hex(void);
unsigned int disco_sdram_bar(enum memory_bank bank);
unsigned int disco_sdram_bs(enum memory_bank bank);
int disco_config_adr_windows(void);
unsigned int disco_winctrl_calcsize(unsigned int sizeval);

#endif /* __ASSEMBLY__ */

#endif /* _DISCOCPU_H */
