/*
 * Copyright 2011 Allied Telesis Labs
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <asm/addrspace.h>
#include <epi3.h>
#include <bootmenu.h>
#include <i2c.h>
#ifdef CONFIG_USB_STORAGE
#include <usb.h>
#endif

#define X510_CORE_CONTROL_REG	0x18000008
#define X510_CAP_REG		0x18000004
#define X510_CLOCK_DIV_REG	0x180000A4
#define ALP_CLOCK		25000000
#define CC_CORECTL_UART_CLKOV_MASK    0x1
#define CC_CAP_UINTCLK		0x00000008  /* UARTs are driven by internal divided clock */
#define CLKD_UART		0x000000ff
#define WDOG_COUNTER		0x18000080
#define CHIP_STATUS		0x1800002c
#define CHIPSTAT_PO_MASK	0x1 /* Package Option */
#define PLL_CONTROLLER_ADDR	0x18000660
#define PLL_CONTROLLER_DATA	0x18000664
#define CORE_CONTROL		0x18000008
#define FLASHSTR_CONFIG		0x1800018c
#define PFLASH_WAITCOUNT	0x1800012c
#define PFLASH_WAITCOUNT_PF1	0x18000130

#define	GPIO_RESET_XG_PHY	1<<0
#define	GPIO_RESET_GBE_PHY	1<<1	/* for Copper models */
#define	GPIO_SFP_INT		1<<1	/* for 28GSX */
#define	GPIO_MANUAL_RST		1<<2
#define	GPIO_PHY_INT		1<<3
#define	GPIO_USB_ENABLE		1<<13

extern uint x510_get_cpu_cap(void);
extern uint x510_get_chipid(void);
int cfi_flash_num_flash_banks;

ulong flash_get_size (phys_addr_t base, int banknum);
extern flash_info_t  flash_info[];


int bootflash_attached = 0;

/* atl_bootrom_board_attached()
 *
 * used by bootmenu to determine weather or not to print
 * option '5' (EPROM) in upgrade bootloader menu
 */

int atl_bootrom_board_attached(void)
{
	return bootflash_attached;
}

/* atl_get_offset_from_base()
 *
 * not needed on this product
 */

u32 atl_get_offset_from_base(void)
{
	return 0;
}

/* atl_get_env_addr()
 *
 * return address of env for places where a macro can't be used.
 */

u32 atl_get_env_addr(void)
{
	return CONFIG_ENV_ADDR;
}

phys_size_t initdram(int board_type)
{
	/* Sdram is setup by assembler code */
	/* If memory could be changed, we should return the true value here */
	return 512 * 1024 * 1024; /* should be 512M must fix */
}

u32 x510_serial_base_clock(void)
{

	uint32_t  w, clock = ALP_CLOCK;

	w = *(u32 *)KSEG1ADDR(X510_CORE_CONTROL_REG);
	if ((w & CC_CORECTL_UART_CLKOV_MASK)) {
		/* internal ALP clock */
		clock = ALP_CLOCK;
	} else {
		w = *(u32 *)KSEG1ADDR(X510_CAP_REG);
		/* Check the clock is internal or external */
		if ((w & CC_CAP_UINTCLK)) {
			/* Internal ALP clock */
			w = *(u32 *)KSEG1ADDR(X510_CLOCK_DIV_REG);
			w = w & CLKD_UART;
			clock = (clock / w);
		}
	}

	return clock;
}


u32 x510_system_counter_freq(void)
{
	u32  w;
	u32 cpu_freq;

	w = *(volatile u32 *)KSEG1ADDR(CHIP_STATUS);
	if (w & CHIPSTAT_PO_MASK) {
		cpu_freq = 400000000;
	} else {
		// return (60000000); /* shorten the delay */
		/* Get N divider to determine CPU clock */
		*(volatile u32 *)KSEG1ADDR(PLL_CONTROLLER_ADDR) = 4;
		w = *(volatile u32 *)KSEG1ADDR(PLL_CONTROLLER_DATA);
		w = ( w & 0x00000fff) >> 3;

		/* Fixed reference clock 25MHz and m = 2 */
		cpu_freq = w * 25000000 / 2;
	}
	return cpu_freq;
}


int checkboard (void)
{
	uint chipid;

	printf("Board: x510\n");

	chipid = x510_get_chipid();
	printf ("Chip revision %04x device %04x, ", (chipid >> 16), (chipid & 0xffff));
	printf("CPU Speed %d MHz\n", (int)(x510_system_counter_freq() /1000/1000));

	return 0;
}


int misc_init_r (void)
{

	/* clear all bits as not using IO pins in special cores */
	*(volatile u32 *)0xb800006c = 0x0000;

	/* Output register enable GPIO13 for USB access */
	*(volatile u32 *)0xb8000064 = 0x2000;

	/* GPIO output enable pins 0, 1, 6, 8, 9, 10,11 and 13 are outputs */
	/* Reset architecture is different between copper and SFP model, but PHY reset (GPIO[1:0])
	release here because interrupt signal is defined as an open-drain */
	*(volatile u32 *)0xb8000068 = 0x2F43;

	/* setup the interrupt inputs, trigger on a high to low signal change */
	*(volatile u32 *)0xb8000074 = 0x00000000;
	*(volatile u32 *)0xb8000070 = 0x1088;

	/* Adjust pointers in epi3 name arrays
	 */
	diag_epi3_reloc_names();
	setenv("ethact", "switch");
#ifdef CONFIG_DIAG_EPI3
	epi3_setmacaddr();
#endif

#ifdef CONFIG_USB_STORAGE
	/* wait for the USB power lane to be stable */
	udelay(100*1000);
	usb_init();
#endif

	/* turn off watchdog timer on RTC device */
	i2c_reg_write(0x68, 0xc, 0x0);

	/* light up 7-segment LED */
	i2c_reg_write(0x20, 0x1, 0x0);	/* output value */
	i2c_reg_write(0x20, 0x3, 0x0);	/* control */

	return 0;
}

u32 x510_flash_init(void)
{
	u32 size;

	size = flash_init();

	return size;
}

u32 atl_get_jffs2_part_size(void)
{
	u32 partition_size = 0;
	int i;

	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
		if (flash_info[i].flash_id != FLASH_UNKNOWN) {
			partition_size += flash_info[i].size;
		}
	}

	if (partition_size != 0) {
		partition_size -= (CONFIG_UBOOT_SIZE + \
				CONFIG_ENV_SECT_SIZE + \
				CONFIG_EPI3_SIZE);
	}
	return partition_size;
}

int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	/* set reset bit */
	*(volatile u32 *)0xb8000064 &= ~GPIO_MANUAL_RST;
	*(volatile u32 *)0xb8000068 |= GPIO_MANUAL_RST;
	return 0;
}

