/*
 * linux/arch/arm/mach-discovery/mpp.h -- Multi Purpose Pins
 *
 * Copyright 2009: Marvell Technology Group Ltd.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301 USA
 */

/* based on include/asm/arch-kirkwood/mpp.h */

#ifndef __DISCOVERY_MPP_H
#define __DISCOVERY_MPP_H

#define MPP(_num, _sel, _in, _out, _SV571) ( \
	/* MPP number */		((_num) & 0xff) | \
	/* MPP select value */		(((_sel) & 0xf) << 8) | \
	/* may be input signal */	((!!(_in)) << 12) | \
	/* may be output signal */	((!!(_out)) << 13) | \
	/* available on SV571 */	((!!(_SV571)) << 14))

#define MPP_NUM(x)	((x) & 0xff)
#define MPP_SEL(x)	(((x) >> 8) & 0xf)

				/*   num sel  i  o  SV5761 */

#define MPP_INPUT_MASK		MPP(  0, 0x0, 1, 0, 0    )
#define MPP_OUTPUT_MASK		MPP(  0, 0x0, 0, 1, 0    )

#define MPP_SV571_MASK		MPP(  0, 0x0, 0, 0, 1    )

#define MPP0_GPIO		MPP(  0, 0x0, 1, 1, 1    )
#define MPP0_GE0_COL		MPP(  0, 0x1, 1, 0, 1    )
#define MPP0_GE1_TXCLK		MPP(  0, 0x2, 0, 1, 1    )

#define MPP1_GPIO		MPP(  1, 0x0, 1, 1, 1    )
#define MPP1_GE0_RXERR		MPP(  1, 0x1, 1, 0, 1    )
#define MPP1_GE1_TXCTL		MPP(  1, 0x2, 0, 1, 1    )

#define MPP2_GPIO		MPP(  2, 0x0, 1, 1, 1    )
#define MPP2_GE0_CRS		MPP(  2, 0x1, 1, 0, 1    )
#define MPP2_GE1_RXCTL		MPP(  2, 0x2, 1, 0, 1    )

#define MPP3_GPIO		MPP(  3, 0x0, 1, 1, 1    )
#define MPP3_GE0_TXERR		MPP(  3, 0x1, 0, 1, 1    )
#define MPP3_GE1_RXCLK		MPP(  3, 0x2, 1, 0, 1    )

#define MPP4_GPIO		MPP(  4, 0x0, 1, 1, 1    )
#define MPP4_GE0_TXD4		MPP(  4, 0x1, 0, 1, 1    )
#define MPP4_GE1_TXD0		MPP(  4, 0x2, 0, 1, 1    )

#define MPP5_GPIO		MPP(  5, 0x0, 1, 1, 1    )
#define MPP5_GE0_TXD5		MPP(  5, 0x1, 0, 1, 1    )
#define MPP5_GE1_TXD1		MPP(  5, 0x2, 0, 1, 1    )

#define MPP6_GPIO		MPP(  6, 0x0, 1, 1, 1    )
#define MPP6_GE0_TXD6		MPP(  6, 0x1, 0, 1, 1    )
#define MPP6_GE1_TXD2		MPP(  6, 0x2, 0, 1, 1    )

#define MPP7_GPIO		MPP(  7, 0x0, 1, 1, 1    )
#define MPP7_GE0_TXD7		MPP(  7, 0x1, 0, 1, 1    )
#define MPP7_GE1_TXD3		MPP(  7, 0x2, 0, 1, 1    )

#define MPP8_GPIO		MPP(  8, 0x0, 1, 1, 1    )
#define MPP8_GE0_RXD4		MPP(  8, 0x1, 1, 0, 1    )
#define MPP8_GE1_RXD0		MPP(  8, 0x2, 1, 0, 1    )

#define MPP9_GPIO		MPP(  9, 0x0, 1, 1, 1    )
#define MPP9_GE0_RXD5		MPP(  9, 0x1, 1, 0, 1    )
#define MPP9_GE1_RXD1		MPP(  9, 0x2, 1, 0, 1    )

#define MPP10_GPIO		MPP( 10, 0x0, 1, 1, 1    )
#define MPP10_GE0_RXD6		MPP( 10, 0x1, 1, 0, 1    )
#define MPP10_GE1_RXD2		MPP( 10, 0X2, 1, 0, 1    )

#define MPP11_GPIO		MPP( 11, 0x0, 1, 1, 1    )
#define MPP11_GE0_RXD7		MPP( 11, 0x1, 1, 0, 1    )
#define MPP11_GE1_RXD3		MPP( 11, 0x2, 1, 0, 1    )

#define MPP12_GPIO		MPP( 12, 0x0, 1, 1, 1    )
#define MPP12_M_BB		MPP( 12, 0x3, 1, 0, 1    )
#define MPP12_UA0_CTSn		MPP( 12, 0x4, 1, 0, 1    )
#define MPP12_NAND_REn0		MPP( 12, 0x5, 0, 1, 1    )

#define MPP13_GPIO		MPP( 13, 0x0, 1, 1, 1    )
#define MPP13_SYSRST_OUTn	MPP( 13, 0x3, 0, 1, 1    )
#define MPP13_UA0_RTSn		MPP( 13, 0x4, 0, 1, 1    )
#define MPP13_NAND_WEn0		MPP( 13, 0x5, 0, 1, 1    )

#define MPP14_GPIO		MPP( 14, 0x0, 1, 1, 1    )
#define MPP14_SATA1_ACTn	MPP( 14, 0x3, 0, 1, 1    )
#define MPP14_UA1_CTSn		MPP( 14, 0x4, 1, 0, 1    )
#define MPP14_NAND_REn1		MPP( 14, 0x5, 0, 1, 1    )

#define MPP15_GPIO		MPP( 15, 0x0, 1, 1, 1    )
#define MPP15_SATA0_ACTn	MPP( 15, 0x3, 0, 1, 1    )
#define MPP15_UA1_RTSn		MPP( 15, 0x4, 0, 1, 1    )
#define MPP15_NAND_WEn1		MPP( 15, 0x5, 0, 1, 1    )

#define MPP16_GPIO		MPP( 16, 0x0, 1, 1, 1    )
#define MPP16_SATA1_PRESENTn	MPP( 16, 0x3, 0, 1, 1    )
#define MPP16_UA2_TXD		MPP( 16, 0x4, 0, 1, 1    )
#define MPP16_NAND_REn3		MPP( 16, 0x5, 0, 1, 1    )

#define MPP17_GPIO		MPP( 17, 0x0, 1, 1, 1    )
#define MPP17_SATA0_PRESENTn	MPP( 17, 0x3, 0, 1, 1    )
#define MPP17_UA2_RXD		MPP( 17, 0x4, 1, 0, 1    )
#define MPP17_NAND_WEn3		MPP( 17, 0x5, 0, 1, 1    )

#define MPP18_GPIO		MPP( 18, 0x0, 1, 1, 1    )
#define MPP18_UA0_CTSn		MPP( 18, 0x4, 1, 0, 1    )
#define MPP18_BOOTNAND_REn	MPP( 18, 0x5, 0, 1, 1    )

#define MPP19_GPIO		MPP( 19, 0x0, 0, 1, 1    )
#define MPP19_UA0_RTSn		MPP( 19, 0x4, 0, 1, 1    )
#define MPP19_BOOTNAME_WEn	MPP( 19, 0x5, 0, 1, 1    )

#define MPP20_GPIO		MPP( 20, 0x0, 1, 1, 1    )
#define MPP20_UA1_CTSn		MPP( 20, 0x4, 1, 0, 1    )

#define MPP21_GPIO		MPP( 21, 0x0, 1, 1, 1    )
#define MPP21_UA1_RTSn		MPP( 21, 0x4, 0, 1, 1    )

#define MPP22_GPIO		MPP( 22, 0x0, 1, 1, 1    )
#define MPP22_UA3_TXD		MPP( 22, 0x4, 0, 1, 1    )
#define MPP22_NAND_REn2		MPP( 22, 0x5, 0, 1, 1    )

#define MPP23_GPIO		MPP( 23, 0x0, 1, 1, 1    )
#define MPP23_UA3_RXD		MPP( 23, 0x4, 1, 0, 1    )
#define MPP23_NAND_WEn2		MPP( 23, 0x5, 0, 1, 1    )

#define MPP24_GPIO		MPP( 24, 0x0, 1, 1, 1    )
#define MPP24_UA2_TXD		MPP( 24, 0x4, 0, 1, 1    )

#define MPP25_GPIO		MPP( 25, 0x0, 1, 1, 1    )
#define MPP25_UA2_RXD		MPP( 25, 0x4, 1, 0, 1    )

#define MPP26_GPIO		MPP( 26, 0x0, 1, 1, 1    )
#define MPP26_UA2_CTSn		MPP( 26, 0x4, 1, 0, 1    )

#define MPP27_GPIO		MPP( 27, 0x0, 1, 1, 1    )
#define MPP27_UA2_RTSn		MPP( 27, 0x4, 1, 0, 1    )

#define MPP28_GPIO		MPP( 28, 0x0, 1, 1, 1    )
#define MPP28_UA3_TXD		MPP( 28, 0x4, 0, 1, 1    )

#define MPP29_GPIO		MPP( 29, 0x0, 1, 1, 1    )
#define MPP29_UA3_RXD		MPP( 29, 0x4, 1, 0, 1    )
#define MPP29_SYSRST_OUTn	MPP( 29, 0x5, 0, 1, 1    )

#define MPP30_GPIO		MPP( 30, 0x0, 1, 1, 1    )
#define MPP3_UA3_CTSn		MPP( 30, 0x4, 1, 0, 1    )

#define MPP31_GPIO		MPP( 31, 0x0, 1, 1, 1    )
#define MPP31_UA3_RTSn		MPP( 31, 0x4, 1, 0, 1    )

#define MPP32_GPIO		MPP( 32, 0x1, 1, 1, 1    )
#define MPP32_UA3_TXD		MPP( 32, 0x4, 0, 1, 1    )
#define MPP32_SYSRST_OUTn	MPP( 32, 0x5, 0, 1, 1    )

#define MPP33_GPIO		MPP( 33, 0x1, 1, 1, 1    )
#define MPP33_UA3_RXD		MPP( 33, 0x4, 1, 0, 1    )

#define MPP34_GPIO		MPP( 34, 0x1, 1, 1, 1    )
#define MPP34_UA2_TXD		MPP( 34, 0x4, 0, 1, 1    )

#define MPP35_GPIO		MPP( 35, 0x1, 1, 1, 1    )
#define MPP35_UA2_RXD		MPP( 35, 0x4, 1, 0, 1    )

#define MPP36_GPIO		MPP( 36, 0x1, 1, 1, 1    )
#define MPP36_UA0_CTSn		MPP( 36, 0x2, 1, 0, 1    )
#define MPP36_UA2_TXD		MPP( 36, 0x4, 0, 1, 1    )

#define MPP37_GPIO		MPP( 37, 0x1, 1, 1, 1    )
#define MPP37_UA0_RTSn		MPP( 37, 0x2, 0, 1, 1    )
#define MPP37_UA2_RXD		MPP( 37, 0x4, 1, 0, 1    )
#define MPP37_SYSRST_OUTn	MPP( 37, 0x5, 0, 1, 1    )

#define MPP38_GPIO		MPP( 38, 0x1, 1, 1, 1    )
#define MPP38_UA1_CTSn		MPP( 38, 0x2, 1, 0, 1    )
#define MPP38_UA3_TXD		MPP( 38, 0x4, 0, 1, 1    )
#define MPP38_SYSRST_OUTn	MPP( 38, 0x5, 0, 1, 1    )

#define MPP39_GPIO		MPP( 39, 0x1, 1, 1, 1    )
#define MPP39_UA1_RTSn		MPP( 39, 0x2, 0, 1, 1    )
#define MPP39_UA3_RXD		MPP( 39, 0x4, 1, 0, 1    )
#define MPP39_SYSRST_OUTn	MPP( 39, 0x5, 0, 1, 1    )

#define MPP40_GPIO		MPP( 40, 0x1, 1, 1, 1    )

#define MPP41_GPIO		MPP( 41, 0x1, 1, 1, 1    )

#define MPP42_GPIO		MPP( 42, 0x1, 1, 1, 1    )

#define MPP43_GPIO		MPP( 43, 0x1, 1, 1, 1    )

#define MPP44_GPIO		MPP( 44, 0x1, 1, 1, 1    )

#define MPP45_GPIO		MPP( 45, 0x1, 1, 1, 1    )
#define MPP45_SATA0_ACTn	MPP( 45, 0x3, 0, 1, 1    )

#define MPP46_GPIO		MPP( 46, 0x1, 1, 1, 1    )

#define MPP47_GPIO		MPP( 47, 0x1, 1, 1, 1    )

#define MPP48_GPIO		MPP( 48, 0x1, 1, 1, 1    )
#define MPP48_SATA1_ACTn	MPP( 48, 0x3, 0, 1, 1    )

#define MPP49_GPIO		MPP( 49, 0x1, 1, 1, 1    )
#define MPP49_SATA0_ACTn	MPP( 49, 0x3, 0, 1, 1    )
#define MPP49_M_BB		MPP( 49, 0x4, 1, 0, 1    )

#define MPP_MAX			49

void discovery_mpp_conf(unsigned int *mpp_list);

#endif
