/*
 * Copyright 2004 Freescale Semiconductor.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * MPC8548PC board configuration file
 *
 */
#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41 */
#define CONFIG_MPC8548		1	/* MPC8548 specific */

#define CONFIG_PCI
#define CONFIG_PCI2		/*rapncsg1 enable PCI2 interface and disable PCI1 interface in u-boot*/
#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_DDR_ECC			/* only for ECC DDR module */
#define CONFIG_MEM_INIT_VALUE	0xdeadbeef
#undef CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
#define CONFIG_RESET_PHY_R		/*MPC8548PC*/

#ifndef __ASSEMBLY__
	extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_SYS_CLK_FREQ	get_clock_freq() /* sysclk for MPC85xx */

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE		    	    /* toggle L2 cache 	*/
#define CONFIG_BTB			    /* toggle branch predition */
#define CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */

#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_R	1	/* Call board early init in ram before flash init*/

#undef	CFG_DRAM_TEST			/* memory test, takes time */
#define CFG_MEMTEST_START	0x00200000	/* memtest works on */
#define CFG_MEMTEST_END		0x00400000

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
#define CFG_CCSRBAR				0xe0000000	/* relocated CCSRBAR */
#define CFG_IMMR					CFG_CCSRBAR	/* PQII uses CFG_IMMR */
#define GEN5_REG					0xe00e0f3c	/* For MPC8548 rev 1.x, GEN5 */

/*
 * DDR Setup
 */
#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE

#define CFG_CS0_BNDS					0x0000000F
#define CFG_CS0_CONFIG				0x80010102
#define CFG_DDR_SDRAM_CLK_CNTL	0x03800000
#define CFG_DDR_IO_OVCR				0x90000000
#define CFG_DDR_DATA_INIT			0xDEADBEEF
#define CFG_TIMING_CFG_0			0x00260802
#define CFG_DDR_SDRAM_MODE2		0x00000000
#define CFG_DDR_SDRAM_MD_CNTL		0x00000000
#define CFG_DDR_SDRAM_CFG			0x43000008
#define CFG_DDR_SDRAM_CFG2			0x04400000
#define CFG_SDRAM_SIZE				256
/*		DDR			400	533	667
		trp	15ns	3		4		5
		tras	45ns	9		12		15
		trcs	15ns	3		4		5
		CL		15ns	3		4		5
		trfc	105ns	21		28		35
		twr	15ns	3		4		5
		trrd	10ns	2		3		4
		twtr	7.5ns	2		2		3
		tfaw	50ns	10		14		17
		trtp	7.5ns	2		2		3
*/
/*Timing for DDR2 400*/
	#define CFG_EXT_REFREC_400				0x00000000
	#define CFG_TIMING_CFG_1_400			0x3935D322
	#define CFG_TIMING_CFG_2_400			0x14904cca
	#define CFG_DDR_SDRAM_MODE_400		0x000a0432
	#define CFG_DDR_SDRAM_INT_400			0x06090100
/*Timing for DDR2 533*/
	#define CFG_EXT_REFREC_533				0x00010000
	#define CFG_TIMING_CFG_1_533			0x4C474432
	#define CFG_TIMING_CFG_2_533			0x13984cce
	#define CFG_DDR_SDRAM_MODE_533		0x000a0442
	#define CFG_DDR_SDRAM_INT_533			0x08000100
/*Timing for DDR2 667*/
	#define CFG_EXT_REFREC_667				0x00020000
	#define CFG_TIMING_CFG_1_667			0x5E593543
	#define CFG_TIMING_CFG_2_667			0x12a06cd1
	#define CFG_DDR_SDRAM_MODE_667		0x000a0452
	#define CFG_DDR_SDRAM_INT_667			0x0a000100
/*
 * Local Bus
 */
#define CFG_FLASH_BASE		0xff000000		/* start of FLASH */
#define CFG_FLASH_BASE1		0xff800000		/* start of FLASH */
#define CFG_BR0_PRELIM		0xff800801
#define CFG_OR0_PRELIM     0xff806f57
#define CFG_BR1_PRELIM		0xff000801		/* port size 8bit	*/
#define CFG_OR1_PRELIM    	0xff006f57

/* For AUTO adjustment of Flash base addresses */
#define CFG_MAX_FLASH_ADJUST	5
#define CFG_MAX_FLASH_TSIZE		BOOKE_PAGESZ_16M
#define CFG_FLASH_BANKS_LIST	{(CFG_FLASH_BASE + 0x800000), CFG_FLASH_BASE}


#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
#define CFG_MAX_FLASH_SECT		135		/* sectors per device */
#undef	CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CFG_LED_BASE    0xf8000000  /* start of LED and Board ID */
#define CFG_BR7_PRELIM  0xf8000801  /* port size 8 bit */
#define CFG_OR7_PRELIM  0xffffef97  /* LED and Board ID */

#define CFG_LBC_LCRR		0x00010008    /* LB clock ratio reg = CCB/8 */
#define CFG_LBC_LCRR2	0x00010002    
#define CFG_LBC_LCRR4	0x00010004    
#define CFG_LBC_BASE		0xf0000000		/* LB base for all the LBC CSx*/

#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */

#define CFG_FLASH_EMPTY_INFO

#undef CONFIG_CLOCKS_IN_MHZ

#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 	1
#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CFG_INIT_RAM_END   0x4000	    /* End of used area in RAM */

#define CFG_GBL_DATA_SIZE  	128	    /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*#define CFG_MONITOR_LEN	    	(256 * 1024) *//* Reserve 256 kB for Mon */
#define CFG_MONITOR_LEN	    	(512 * 1024)	/* Reserve 512 kB for u-boot size */
#define CFG_MALLOC_LEN	    	(128 * 1024)	/* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_INDEX     1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE    1
#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)

/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef  CFG_HUSH_PARSER
	#define CFG_PROMPT_HUSH_PS2 "> "
#endif

/* I2C */
#define CONFIG_HARD_I2C			/* I2C with hardware support */
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
#define CFG_I2C_SPEED			400000	/* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR	0x57
#define CFG_I2C_SLAVE			0x7F
#define CFG_I2C_NOPROBES      {0x69}	/* Don't probe these addrs */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CFG_PCI1_MEM_BASE	0x80000000
#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CFG_PCI1_IO_BASE	0xe2000000
#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE	0x800000	/* 8M */

#define CFG_PCI2_MEM_BASE	0x90000000
#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
#define CFG_PCI2_MEM_SIZE	0x10000000	/* 256M */
#define CFG_PCI2_IO_BASE	0xe2800000
#define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
#define CFG_PCI2_IO_SIZE	0x800000	/* 8M */

#define CFG_PEX_MEM_BASE	0xa0000000
#define CFG_PEX_MEM_PHYS	CFG_PEX_MEM_BASE
#define CFG_PEX_MEM_SIZE	0x20000000	/* 512M */
#define CFG_PEX_IO_BASE		0xe3000000
#define CFG_PEX_IO_PHYS		CFG_PEX_IO_BASE
#define CFG_PEX_IO_SIZE		0x1000000	/* 16M */

/* 
 * RapidIO 
 */
#define CFG_RIO_MEM_BASE	0xC0000000
#define CFG_RIO_MEM_SIZE	0x20000000

#if defined(CONFIG_PCI)

	#define CONFIG_NET_MULTI
	#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */

	#undef CONFIG_EEPRO100
	#undef CONFIG_TULIP

	#if !defined(CONFIG_PCI_PNP)
    	#define PCI_ENET0_IOADDR      0xe0000000
    	#define PCI_ENET0_MEMADDR     0xe0000000
    	#define PCI_IDSEL_NUMBER      0x0e 	/*(IDSEL)=14*/
	#endif

	#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
	#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */


#if defined(CONFIG_TSEC_ENET)

	#ifndef CONFIG_NET_MULTI
		#define CONFIG_NET_MULTI 	1
	#endif

	#define CONFIG_MII		1	/* MII PHY management */
	#define CONFIG_MPC85XX_TSEC1	1
	#define CONFIG_MPC85XX_TSEC2	1
	#define CONFIG_MPC85XX_TSEC3	1
	#define TSEC1_PHY_ADDR		4
	#define TSEC2_PHY_ADDR		5
	#define TSEC3_PHY_ADDR		3
	#define TSEC1_PHYIDX		0
	#define TSEC2_PHYIDX		0
	#define TSEC3_PHYIDX		0

	/* MPC8548PC ,  the on board ethernet*/
	#define CONFIG_MPC85XX_TSEC1_NAME       "eTSEC0"
	#define CONFIG_MPC85XX_TSEC2_NAME       "eTSEC1"
	#define CONFIG_MPC85XX_TSEC3_NAME       "eTSEC2"

	/*For compability between different Type-N, Type-A, Type-S Carrier, only three eTSEC is defined*/
	#if 1
		#define CONFIG_MPC85XX_TSEC4	1
		#define TSEC4_PHY_ADDR		6 
		#define TSEC4_PHYIDX		0
		#define CONFIG_MPC85XX_TSEC4_NAME       "eTSEC3"
	#endif

#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#define CFG_ENV_IS_IN_FLASH	1
/*Set ENV at address 0xFFF70000 - 0xFFF7FFFF*/
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x10000)
#define CFG_ENV_SECT_SIZE	0x10000	/* 64K for env */
#define CFG_ENV_SIZE		0x2000

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C | CFG_CMD_MII | CFG_CMD_PCI | CFG_CMD_NET)
#include <cmd_confdefs.h>

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	*/
#define CFG_LOAD_ADDR	0x1000000	/* default load address */
#define CFG_PROMPT	get_prompt()	/* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
#else
	#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux*/

/* Cache Configuration */
#define CFG_DCACHE_SIZE	32768
#define CFG_CACHELINE_SIZE	32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot */

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
	#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
	#define CONFIG_ETHADDR   00:E0:0C:48:00:04
	#define CONFIG_HAS_ETH1
	#define CONFIG_ETH1ADDR  00:E0:0C:48:01:04
	#define CONFIG_HAS_ETH2
	#define CONFIG_ETH2ADDR  00:E0:0C:48:02:04
	#define CONFIG_HAS_ETH3
	#define CONFIG_ETH3ADDR  00:E0:0C:48:03:04
#endif

#define CONFIG_IPADDR    10.196.31.201

#define CONFIG_HOSTNAME		MPC8548PC
#define CONFIG_ROOTPATH		/nfsroot
#define CONFIG_BOOTFILE		uImage8548

#define CONFIG_SERVERIP  10.196.31.38
#define CONFIG_GATEWAYIP 10.196.31.254
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  1000000   /*default location for tftp and bootm*/

#define CONFIG_BOOTDELAY 2       /* -1 disables auto-boot */

#define CONFIG_BAUDRATE	115200

#define	CONFIG_EXTRA_ENV_SETTINGS				        \
   "netdev=eth0\0"                                                      \
   "consoledev=ttyS0\0"                                                 \
   "ramdiskaddr=1200000\0"                                               \
   "ramdiskfile=jramdisk\0"												\
   "hddev=sda3\0"								\
   "hdboot=setenv bootargs root=/dev/$hddev rw console=$consoledev,$baudrate; bootm ff800000\0" \
   "fname=u-boot-1.1.2.8540.pc\0"				\
   "fub=tftp 1000000 $fname;erase ff780000 ff7fffff;cp.b 1000000 ff780000 80000"

#define CONFIG_NFSBOOTCOMMAND	                                        \
	"ethact=eTSEC2\0"									\
   "setenv bootargs root=/dev/nfs rw "                                  \
      "nfsroot=$serverip:$rootpath "                                    \
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $loadaddr $bootfile;"                                          \
   "bootm $loadaddr"

#define CONFIG_RAMBOOTCOMMAND \
	"ethact=eTSEC2\0"									\
   "setenv bootargs root=/dev/ram rw "                                  \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $ramdiskaddr $ramdiskfile;"                                    \
   "tftp $loadaddr $bootfile;"                                          \
   "bootm $loadaddr $ramdiskaddr"

#define CONFIG_BOOTARGS      "root=/dev/ram rw console=ttyS0,115200" 

#define CONFIG_BOOTCOMMAND  CONFIG_RAMBOOTCOMMAND

#endif	/* __CONFIG_H */
