/*
 * x600.h
 * Matthew Millman
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#undef DEBUG
/*
 * High level platform definition
 */
 
#define CONFIG_X600
#define CONFIG_DIAGNOSTICS
#define CONFIG_DIAG_NOR_FLASH
#define CONFIG_DIAG_EPI3
#define CONFIG_COMPATIBLE_DEVICES       \
{                                       \
    { 289, "x600-24Ts" },               \
    { 290, "x600-24Ts/XP" },            \
    { 293, "x600-48Ts" },               \
    { 294, "x600-48Ts/XP" },            \
    { 325, "x600-24Ts-PoE" },           \
    { 326, "x600-24Ts-PoE+" },          \
    { 0, NULL }                         \
}
#define CONFIG_THIS_DEVICE  6

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 Family */
#define CONFIG_MPC83xx		1	/* MPC83XX family */
#define CONFIG_MPC834x		1	/* MPC834x family */
#define CONFIG_MPC8347E		1	/* MPC8347E specific */
#define CPU_ID_STR		"MPC8347E"

#define CONFIG_PCI
#undef CONFIG_MPC83XX_PCI2 		/* support for 2nd PCI controller */

#define CONFIG_83XX_CLKIN	66666000	/* in Hz */


#define CONFIG_SYS_CLK_FREQ	66666000
#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1

#define CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
#define CONFIG_MISC_INIT_R

#define CONFIG_SYS_IMMR		0xEC000000

#undef CONFIG_SYS_DRAM_TEST				/* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START	0x00000000      /* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00100000

/*
 * DDR Setup
 */
#define CONFIG_DDR_ECC
#define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */


#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#undef  CONFIG_DDR_2T_TIMING

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
//#define CONFIG_SYS_FLASH_CFI_DRIVER			/* use the CFI driver */
#define CONFIG_SYS_FLASH_BASE		0xF0000000	/* start of FLASH   */
#define CONFIG_SYS_FLASH_SIZE		64		/* flash size in MB */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { { CONFIG_SYS_FLASH_BASE, 0x100000 } }

#define CONFIG_SYS_CPLD_BASE		0xEE000000

#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_MONITOR_BASE /* window base at flash base */
#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000016	 /* 8 MB window size */

#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	515		/* sectors per device */

#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MID_FLASH_JUMP	0x7F000000
#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef  CONFIG_SYS_RAMBOOT
#endif


#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000		/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END	0x2000			/* End of used area in RAM*/

#define CONFIG_SYS_GBL_DATA_SIZE	0x100			/* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Defines used by bootmenu
 */
#define CONFIG_BOOTMENU 
#define CONFIG_UBOOT_ROM_BASE   CONFIG_SYS_FLASH_BASE
#define CONFIG_DIAGMEM_BASE     0x1000000
#define CONFIG_UBOOT_SIZE	0xC0000
#define CONFIG_UBOOT_FLASH_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_NVS_LOCATION 	0xEF000000
#define CONFIG_NVS_SIZE		0x80000
#define CONFIG_SYS_STDALONE_TFTP

/*
 * OR/BR Registers
 */

#define CONFIG_SYS_BR0_PRELIM		CONFIG_SYS_FLASH_BASE | 0x00001001	/* FLASH */
// Default: Very slow timing (44 clocks/cycle)
//#define CONFIG_SYS_OR0_PRELIM		0xFC006FF7
// Should be OK for chips up to 135ns access time (7 clocks/cycle)
#define CONFIG_SYS_OR0_PRELIM		0xFC000E30


#define CONFIG_SYS_BR1_PRELIM		CONFIG_SYS_CPLD_BASE | 0x801 		/* ATI's CPLD @ 0xEE000000 */
#define CONFIG_SYS_OR1_PRELIM		0xFFFFEFF7

#define CONFIG_SYS_BR2_PRELIM		CONFIG_NVS_LOCATION | 0x801	/* SRAM/NVS */
#define CONFIG_SYS_OR2_PRELIM		0xFFF86FF7

/* 
 * LAW Registers
 */

#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SYS_LBLAWAR1_PRELIM	0x80000013	/* 1MB */

#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH */
#define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000019	/* 64MB */

#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_CPLD_BASE	/* CPLD & SRAM */
#define CONFIG_SYS_LBLAWAR3_PRELIM	0x80000018	/* 32MB */

/*
 * Local Bus LCRR and LBCR regs
 *    LCRR:  DLL bypass, Clock divider is 4
 * External Local Bus rate is
 *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 */
#define CONFIG_SYS_LCRR	(LCRR_DBYP | LCRR_CLKDIV_8)
#define CONFIG_SYS_LBC_LBCR	0x00000000

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX     1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE    1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)


/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C			/* I2C with hardware support*/
#undef CONFIG_SOFT_I2C			/* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED		80000	/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_OFFSET		0x3000
#define CONFIG_SYS_I2C2_OFFSET		0x3100
#define CONFIG_I2C_MULTI_BUS		1
#define CONFIG_FSL_I2C_CUSTOM_DFSR	0x10
#define CONFIG_RTC_DS1338

/* TSEC */
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)

/* USB */
//#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY	1 /* Use SYS board PHY */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */

#define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI2_IO_BASE	0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS	0xE2100000
#define CONFIG_SYS_PCI2_IO_SIZE	0x00100000	/* 1M */

#if defined(CONFIG_PCI)

#define PCI_ONE_PCI1
#if defined(PCI_64BIT)
#undef PCI_ALL_PCI1
#undef PCI_TWO_PCI1
#undef PCI_ONE_PCI1
#endif

#define CONFIG_NET_MULTI
//#define CONFIG_PCI_PNP		/* do pci plug-and-play */

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */

/*
 * TSEC configuration
 */
#define CONFIG_TSEC_ENET		/* TSEC ethernet support */
#define CONFIG_ETH_SWITCH		/* Boot from switch ports */

#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI	1
#endif

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_GMII		1	/* MII PHY management */
#define CONFIG_MPC83XX_TSEC1	1
#define CONFIG_MPC83XX_TSEC1_NAME	"TSEC0"
#define TSEC1_PHY_ADDR		0x21
#define TSEC1_PHYIDX		0

#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0xC0000)
#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
#define CONFIG_ENV_SIZE		0x2000
#define ATL_CFG_ENV_LOCATION_NOT_FIXED

/*
 * EPI3 block
 */
#define CONFIG_EPI3_SIZE        0x00020000
#define CONFIG_EPI3_LOCATION    (CONFIG_SYS_FLASH_BASE + 0xE0000)

/*
 * JFFS2 boundaries
 */
#define CONFIG_JFFS2_PART_OFFSET 0x100000
#define CONFIG_JFFS2_PART_SIZE   (atl_get_jffs2_part_size())
#define DIAG_USER_FLASH_OFFSET		CONFIG_JFFS2_PART_OFFSET
#define DIAG_USER_FLASH_SIZE		CONFIG_JFFS2_PART_SIZE

/*
 * Removable storage
 */

#define CONFIG_MMC_SPI
#define CONFIG_SPI
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#define CONFIG_MMC_MAX_FREQ	25000000

#include <configs/atl-std-opts.h>

#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#include <config_cmd_default.h>

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_PROMPT	"x600> "	/* Monitor Command Prompt */
#define CONFIG_DOS_PARTITION

/* Cache Configuration */
#define CONFIG_SYS_DCACHE_SIZE		32768
#define CONFIG_SYS_CACHELINE_SIZE	32
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
#endif

#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */

#if 1 /*528/264*/
#define CONFIG_SYS_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_1X1 |\
	HRCWL_CSB_TO_CLKIN |\
	HRCWL_VCO_1X2 |\
	HRCWL_CORE_TO_CSB_1_5X1)
#elif 0 /*396/132*/
#define CONFIG_SYS_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_1X1 |\
	HRCWL_CSB_TO_CLKIN |\
	HRCWL_VCO_1X4 |\
	HRCWL_CORE_TO_CSB_3X1)
#elif 0 /*264/132*/
#define CONFIG_SYS_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_1X1 |\
	HRCWL_CSB_TO_CLKIN |\
	HRCWL_VCO_1X4 |\
	HRCWL_CORE_TO_CSB_2X1)
#elif 0 /*132/132*/
#define CONFIG_SYS_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_1X1 |\
	HRCWL_CSB_TO_CLKIN |\
	HRCWL_VCO_1X4 |\
	HRCWL_CORE_TO_CSB_1X1)
#elif 0 /*264/264 */
#define CONFIG_SYS_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_1X1 |\
	HRCWL_CSB_TO_CLKIN |\
	HRCWL_VCO_1X4 |\
	HRCWL_CORE_TO_CSB_1X1)
#endif

#if defined(PCI_64BIT)
#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_64_BIT_PCI |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_PCI2_ARBITER_DISABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_TSEC1M_IN_GMII |\
	HRCWH_TSEC2M_IN_GMII )
#else
#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_32_BIT_PCI |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_PCI2_ARBITER_ENABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_TSEC1M_IN_GMII |\
	HRCWH_TSEC2M_IN_GMII )
#endif

/* System IO Config */
#define CONFIG_SYS_SICRH SICRH_TSOBI1 | SICRH_TSEC2_A | SICRH_TSEC2_B | SICRH_TSEC2_C | SICRH_TSEC2_D | \
				 SICRH_TSEC2_E | SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H
#define CONFIG_SYS_SICRL SICRL_LDP_A

#define CONFIG_SYS_HID0_INIT	(HID0_ENABLE_MACHINE_CHECK | HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | HID0_ENABLE_INSTRUCTION_CACHE)


/* #define CONFIG_SYS_HID0_FINAL		(\
	HID0_ENABLE_INSTRUCTION_CACHE |\
	HID0_ENABLE_M_BIT |\
	HID0_ENABLE_ADDRESS_BROADCAST ) */


#define CONFIG_SYS_HID2 HID2_HBE

/* DDR @ 0x00000000 (0-255MB) */
#define CONFIG_SYS_IBAT0L	(0x00000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(0x00000000 | BATU_BL_256M | BATU_VS | BATU_VP)

/* DDR @ 0x10000000 (256-512MB) */
#define CONFIG_SYS_IBAT1L	(0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U	(0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)


/* PCI @ 0x80000000 */
#ifdef CONFIG_PCI
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#else
#define CONFIG_SYS_IBAT2L	(0)
#define CONFIG_SYS_IBAT2U	(0)
#define CONFIG_SYS_IBAT3L	(0)
#define CONFIG_SYS_IBAT3U	(0)
#endif

#define CONFIG_HIGH_BATS

#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_1M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT4L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_1M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_FLASH_BASE | BATU_BL_64M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_WRITETHROUGH | BATL_MEMCOHERENCE | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT5U	(CONFIG_SYS_FLASH_BASE | BATU_BL_64M | BATU_VS | BATU_VP)

/* IMMR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_IMMR | BATU_BL_64M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT7L	(0)
#define CONFIG_SYS_IBAT7U	(0)

#define CONFIG_SYS_DBAT7L	(0)
#define CONFIG_SYS_DBAT7U	(0)

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U


#endif	/* __CONFIG_H */
