/* MII common registers
 */
#define PHY_MII_REG_CONTROL      0
#define PHY_MII_REG_STATUS       1
#define PHY_MII_REG_PHYID_1      2
#define PHY_MII_REG_PHYID_2      3
#define PHY_MII_REG_AUTONEG_ADV  4
#define PHY_MII_REG_AUTONEG_LPA  5
#define PHY_MII_REG_AUTONEG_EXT  6

#define PHY_MII_REGAD_MASK       0x1F		/*Defines largest MII reg address*/

/* Control register (0) */
#define PHY_MII_REG_C_RESET      0x8000		/*Self-clearing bit*/
#define PHY_MII_REG_C_LOOPBACK   0x4000
#define PHY_MII_REG_C_100MBPS    0x2000
#define PHY_MII_REG_C_AUTONEG    0x1000
#define PHY_MII_REG_C_POWERDOWN  0x0800
#define PHY_MII_REG_C_ISOLATE    0x0400
#define PHY_MII_REG_C_ANEG_RST   0x0200
#define PHY_MII_REG_C_FULLDUPLEX 0x0100

/* Status register (1) */
#define PHY_MII_REG_S_ANCOMPLETE 0x0020
#define PHY_MII_REG_S_LINK_UP    0x0004		/*Latches low, reset by read*/
#define PHY_MII_REG_S_AUTO_NEG   0x0020


/* PHY Identification register 1 (2) */
#define PHY_MII_REG_I1_LXT970    0x7810		/*Level One LXT970, LXT970A*/
#define PHY_MII_REG_I1_KS8737    0x0022		/*Kendin KS8737*/
#define PHY_MII_REG_I1_LAN91C111 0x0016		/*SMSC LAN91C111*/
#define PHY_MII_REG_I1_AC101L	 0x786d		/* Altima/Broadcom AC101L */

/* PHY Autonegotiaon advertisement register (4) */
#define PHY_MII_REG_AD_NEXTPAGE	 0x8000
#define PHY_MII_REG_AD_PAUSE	 0x0400
#define PHY_MII_REG_AD_100BT4 	 0x0200
#define PHY_MII_REG_AD_100BTX_FD 0x0100
#define PHY_MII_REG_AD_100BTX	 0x0080
#define PHY_MII_REG_AD_10BTX_FD	 0x0040
#define PHY_MII_REG_AD_10BTX	 0x0020
#define PHY_MII_REG_AD_802_3	 0x0001

/* Auto Negotiation Link Partner Ability register (5) */
#define PHY_MII_REG_AL_ACK       0x4000
#define PHY_MII_REG_AL_100TXFD   0x0100
#define PHY_MII_REG_AL_100TXHD   0x0080
#define PHY_MII_REG_AL_10TFD     0x0040
#define PHY_MII_REG_AL_10THD     0x0020

/* Auto Negotiation Expansion register (6) */
#define PHY_MII_REG_AE_PDFAULT   0x0010
#define PHY_MII_REG_AE_ANABLE    0x0001

/* Altima AC101L PHY */

#define AC101L_REG_INT_CTRL_STAT		17
#define AC101L_REG_CABLE_MES			20
#define AC101L_REG_OPER_MODE			23
#define AC101L_REG_PHYMODE				28

/* Interrupt control & status (17) */
#define AC101L_REG_I_PDF_EN				0x1000
#define AC101L_REG_I_LINK_EN			0x0400
#define AC101L_REG_I_ANCOMP_EN			0x0100

/* Operation Mode (23) */
#define AC101L_REG_O_DIS_AUTO_MDI		0x0080
#define AC101L_REG_O_MDI_MDIX			0x0040

/* Phy mode control reg (28) */
#define AC101L_REG_PAGE_MASK			0xF000
#define AC101L_REG_PAGE0				0x0000
#define AC101L_REG_PAGE1				0x1000
#define AC101L_REG_PAGE2				0x2000
#define AC101L_REG_PAGE3				0x3000

/* Various paged registers that rely on the phy mode control reg */
#define AC101L_REG_PG0_TESTMODE			29
#define AC101L_REG_PG1_LED_BLINK		29
#define AC101L_REG_PG1_LED0_SETTING1	30
#define AC101L_REG_PG1_LED0_SETTING2	31
#define AC101L_REG_PG2_LED1_SETTING1	29
#define AC101L_REG_PG2_LED1_SETTING2	30
#define AC101L_REG_PG2_LED2_SETTING1	31
#define AC101L_REG_PG3_LED2_SETTING2	29
#define AC101L_REG_PG3_LED3_SETTING1	30
#define AC101L_REG_PG3_LED3_SETTING2	31

/* LED settings */
#define AC101L_LED_EVENT_DUP		0x80
#define AC101L_LED_EVENT_COL		0x40
#define AC101L_LED_EVENT_100		0x20
#define AC101L_LED_EVENT_10			0x10
#define AC101L_LED_EVENT_TX			0x08
#define AC101L_LED_EVENT_TXRX		0x04
#define AC101L_LED_EVENT_RX			0x02
#define AC101L_LED_EVENT_LINK		0x01
#define AC101L_LED_ON_SHIFT			8
#define AC101L_LED_ON_EVENT_DUP		(AC101L_LED_EVENT_DUP << AC101L_LED_ON_SHIFT)	
#define AC101L_LED_ON_EVENT_COL		(AC101L_LED_EVENT_COL << AC101L_LED_ON_SHIFT)	
#define AC101L_LED_ON_EVENT_100		(AC101L_LED_EVENT_100 << AC101L_LED_ON_SHIFT)	
#define AC101L_LED_ON_EVENT_10		(AC101L_LED_EVENT_10  << AC101L_LED_ON_SHIFT)		
#define AC101L_LED_ON_EVENT_TX		(AC101L_LED_EVENT_TX  << AC101L_LED_ON_SHIFT)		
#define AC101L_LED_ON_EVENT_TXRX	(AC101L_LED_EVENT_TXRX << AC101L_LED_ON_SHIFT)
#define AC101L_LED_ON_EVENT_RX		(AC101L_LED_EVENT_RX   << AC101L_LED_ON_SHIFT)		
#define AC101L_LED_ON_EVENT_LINK	(AC101L_LED_EVENT_LINK << AC101L_LED_ON_SHIFT)

#define MIIM_CONTROL            0x00
#define MIIM_CONTROL_RESET	0x9140
#define MIIM_CONTROL_INIT       0x1140
#define MIIM_CONTROL_RESTART    0x1340
#define MIIM_ANEN               0x1000

#define MIIM_CR                 0x00
#define MIIM_CR_RST		0x8000
#define MIIM_CR_INIT	        0x1000

#define MIIM_STATUS		0x1
#define MIIM_STATUS_AN_DONE 	0x0020
#define MIIM_STATUS_LINK	0x0004
#define PHY_BMSR_AUTN_ABLE	0x0008
#define PHY_BMSR_AUTN_COMP	0x0020

#define MIIM_PHYIR1		0x2
#define MIIM_PHYIR2		0x3

#define MIIM_ANAR		0x4
#define MIIM_ANAR_INIT		0x1e1



void atl_ar440_miiphy_init (void);

int atl_ar440_miiphy_write (char *devname, unsigned char device,
		unsigned char regId, unsigned short value, unsigned char type);
		
int atl_ar440_miiphy_read (char *devname, unsigned char device,
		unsigned char regId, unsigned short *value);
		
				
		
